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AS7C31026B-12TCN Datasheet

  • AS7C31026B-12TCN

  • 3.3 V 64K X 16 CMOS SRAM

  • 123.62KB

  • 10頁

  • ALSC

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March 2004
廬
AS7C31026B
3.3 V 64K X 16 CMOS SRAM
Features
鈥?Industrial and commercial versions
鈥?Organization: 65,536 words 脳 16 bits
鈥?Center power and ground pins for low noise
鈥?High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
鈥?Low power consumption: ACTIVE
- 288 mW / max @ 10 ns
鈥?Easy memory expansion with
CE
,
OE
inputs
鈥?TTL-compatible, three-state I/O
鈥?JEDEC standard packaging
鈥?ESD protection
鈮?/div>
2000 volts
鈥?Latch-up current
鈮?/div>
200 mA
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
鈥?Low power consumption: STANDBY
- 18 mW / max CMOS I/O
鈥?6 T 0.18 u CMOS technology
Logic block diagram
A0
Pin arrangement
V
CC
A2
A3
A4
A5
A6
A7
I/O0鈥揑/O7
I/O8鈥揑/O15
Row decoder
A1
44-Pin SOJ (400 mil), TSOP 2
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
64 K 脳 16
Array
GND
WE
Column decoder
A8
A9
A10
A11
A12
A13
A14
A15
UB
OE
LB
CE
Selection guide
-10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
-12
12
6
75
5
-15
15
7
70
5
AS7C31026B
I/O
buffer
Control circuit
-20
20
8
65
5
Unit
ns
ns
mA
mA
10
5
80
5
3/26/04, v 1.3
Alliance Semiconductor
P. 1 of 10
Copyright 漏 Alliance Semiconductor. All rights reserved.

AS7C31026B-12TCN 產(chǎn)品屬性

  • Alliance Memory

  • 1 Mbit

  • 64 K x 16

  • 12 ns

  • 3.6 V

  • 3 V

  • 5 mA

  • + 70 C

  • 0 C

  • SMD/SMT

  • TSOP-44

  • Tray

  • Parrallel

  • 83 MHz

  • 135

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