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AS7C252MPFS18A-166TQIN Datasheet

  • AS7C252MPFS18A-166TQIN

  • 2.5V 2M x 18 pipelined burst synchronous SRAM

  • 18頁

  • ALSC

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February 2005
廬
AS7C252MPFS18A
2.5V 2M
脳
18 pipelined burst synchronous SRAM
Features
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Organization: 2,097,152 words 脳 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.1/3.5/3.8 ns
Fast OE access time: 3.1/3.5/3.8 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
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Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[20:0]
CLK
CS
CLR
Burst logic
Q
21
CS
Address
D
21
19 21
2M x 18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
CLK
D
registers
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.1
450
170
90
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
2/14/05, v.1.3
Alliance Semiconductor
1 of 18
Copyright 漏 Alliance Semiconductor. All rights reserved.

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