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AS7C252MNTD18A-133TQCN Datasheet

  • AS7C252MNTD18A-133TQCN

  • 2.5V 2M x 18 Pipelined SRAM with NTD

  • 18頁

  • ALSC

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January 2005
廬
AS7C252MNTD18A
2.5V 2M 脳 18 Pipelined SRAM with NTD
TM
Features
鈥?Organization: 2,097,152 words 脳 18 bits
鈥?NTD
鈩?/div>
architecture for efficient bus operation
鈥?Fast clock speeds to 200 MHz
鈥?Fast clock to data access: 3.2/3.5/3.8 ns
鈥?Fast OE access time: 3.2/3.5/3.8 ns
鈥?Fully synchronous operation
鈥?Pipelined mode
鈥?Common data inputs and data outputs
鈥?Asynchronous output enable control
Logic block diagram
A[20:0]
21
D
鈥?Available in 100-pin TQFP packages
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?2.5V core power supply
鈥?Self-timed write cycles
鈥?Interleaved or linear burst modes
鈥?Snooze mode for standby operation
Address
register
Burst logic
Q
21
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
CLK
D
Q
21
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
2 M x 18
SRAM
Array
DQ[a,b]
18
D
Data
Q
Input
Register
CLK
18
18
18
18
CLK
CEN
CLK
OE
Output
Register
18
OE
DQ[a,b]
Selection guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.2
450
170
90
-166
6
166
3.5
400
150
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
1/17/05, V 1.2
Alliance Semiconductor
P. 1 of 18
Copyright 漏 Alliance Semiconductor. All rights reserved.

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