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AS7C251MNTF18A-75TQIN Datasheet

  • AS7C251MNTF18A-75TQIN

  • 2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD

  • 18頁(yè)

  • ALSC

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December 2004
廬
AS7C251MNTF18A
2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD
TM
Features
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Organization: 1,048,576 words 脳 18 bits
NTD
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architecture for efficient bus operation
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP package
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Individual byte write and global write
Clock enable for operation hold
Multiple chip enables for easy expansion
2.5V core power supply
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[19:0]
20
D
Address
register
burst logic
Q
20
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D
Q
20
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
1M x 18
SRAM
array
DQ [a,b]
18
D
Data
Q
input
register
CLK
18
18
18
18
CLK
CEN
OE
Output
buffer
18
OE
DQ [a,b]
Selection guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
275
90
60
-85
10
8.5
250
80
60
-10
12
10
230
80
60
Units
ns
ns
mA
mA
mA
12/23/04, v 1.1
Alliance Semiconductor
P. 1 of 18
Copyright 漏 Alliance Semiconductor. All rights reserved.

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