鈥?/div>
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
CLK
CS
CLR
Burst logic
Q
20
CS
Address
D
20
18 20
1M
x
18
Memory
array
18
18
register
CLK
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
D
ZZ
Enable
register
Q
Output
buffers
Input
registers
CLK
Power
down
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
275
90
60
-85
10
8.5
250
80
60
-10
12
10
230
80
60
Units
ns
ns
mA
mA
mA
12/24/04, v. 1.2
Alliance Semiconductor
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