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AS7C31024L-15TJC Datasheet

  • AS7C31024L-15TJC

  • x8 SRAM

  • 10頁

  • ETC

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鈥?Organization: 131,072 words 脳 8 bits
鈥?High speed
- 10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
鈥?Low power consumption available
- Active: 180 mW max (3V, 15 ns)
- Standby: 1.8 mW max, CMOS I/O
- Very low DC component in active power
鈥?2.0V data retention
鈥?Equal access and cycle times
鈥?Easy memory expansion with CE1, CE2, OE inputs
鈥?TTL/LVTTL-compatible, three-state I/O
鈥?32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
Socket compatible with 7C512 (64K脳8)
- 400 mil SOJ
- 8mm 脳 20mm TSOP
鈥?ESD protection
鈮?/div>
2000 volts
鈥?Latch-up current
鈮?/div>
200 mA
鈥?3.3V and 5.0V versions available
鈥?Industrial and commercial temperature available
鈥?Intelliwatt
tm
low power and CPG versions available
65$0
/RJLFEORFNGLDJUDP
Vcc
GND
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
3LQDUUDQJHPHQW
TSOP
DIP, SOJ
I/O7
Row decoder
512脳256脳8
Array
(1,048,576)
Sense amp
I/O0
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
NC
A10
CE1
A16
I/O7
A14
I/O6
A12
A7
I/O5
I/O4
A6
I/O3
A5
GND
A4
I/O2
A3
I/O1
A2
I/O0
A1
A0
A0
A1
I/O0
A2
I/O1
A3
Column decoder
Control
circuit
WE
OE
CE1
CE2
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
6HOHFWLRQJXLGH
-10
Maximum address access time
Maximum output enable access time
AS7C1024
Maximum operating current
AS7C1024L
AS7C31024
AS7C31024L
Maximum static standby current (L)
Shaded areas contain advance information.
A9
A10
A11
A12
A13
A14
A15
A16
-12
12
3
160
120
100
60
0.1
-15
15
4
120
95
70
50
0.1
-20
20
5
110
80
65
45
0.1
Unit
ns
ns
mA
mA
mA
mA
mA
10
3
175
鈥?/div>
150
鈥?/div>
0.1
',' % 
','  %  
$//,$1&(6(0,&21'8&725

Copyright 漏1998 Alliance Semiconductor. All rights reserved.
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