鈮?/div>
200 mA
- 48-ball FBGA
- 400-mil 44-pin TSOP II
鈥?Low power consumption: STANDBY
- 66 碌W max at 3.3V
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1鈥揑/O8
I/O9鈥揑/O16
WE
Row Decoder
V
CC
256K 脳 16
Array
(4,194,304)
V
SS
Pin arrangement (top view)
44-pin 400-mil TSOP II
A4
1
A5
44
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
5
A0
UB
40
LB
6
39
CS
I/O16
I/O1
7
38
I/O15
I/O2
8
37
I/O14
I/O3
9
36
I/O13
I/O4
10
35
V
CC
V
SS
11
34
V
SS
V
CC
12
33
I/O5
13
32
I/O12
I/O6
I/O11
14
31
I/O7
I/O10
15
30
I/O8
I/O9
16
29
WE
NC
17
28
A17
18
A8
27
A16
A9
19
26
A15
20
25
A10
A14
21
A11
24
A13
22
A12
23
Note: A 鈥淢ODE鈥?pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to V
CC
or V
SS
configures the device. There should
only be 44+2+2 pads on the chip. Two extra V
CC
to separate out Array from
Peripheral and Two-Mode Pads.
I/O
buffer
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
UB
OE
LB
CS
48-CSP Ball-Grid-Array Package
A
B
C
D
E
F
G
H
1
LB
I/O9
I/O10
V
SS
V
CC
I/O15
I/O16
NC
2
3
OE
A0
A3
UB
I/O11 A5
I/O12 A17
I/O13 NC
I/O14 A14
NC
A12
A8
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
I/O2
I/O4
I/O5
I/O6
WE
A11
6
NC
I/O1
I/O3
V
CC
V
SS
I/O7
I/O8
NC
Selection guide
V
CC
Range
Product
AS6VA25616
Min
(V)
2.7
Typ
2
(V)
3.0
Max
(V)
3.3
Speed
(ns)
55
Power Dissipation
Operating (I
CC1
)
Max (mA)
2
Standby (I
SB2
)
Max (
碌
A)
20
8/31/00
ALLIANCE SEMICONDUCTOR
1
Copyright 漏2000 Alliance Semiconductor. All rights reserved.