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AS5SS256K36A Datasheet

  • AS5SS256K36A

  • 256K x 36 SSRAM Flow-Through. Synchronous Burst SRAM

  • 324.47KB

  • 16頁

  • ETC

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Austin Semiconductor, Inc.
256K x 36 SSRAM
Flow-Through, Synchronous
Burst SRAM
FEATURES
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AS5SS256K36 &
AS5SS256K36A
PIN ASSIGNMENT
(Top View)
SSRAM
100-pin TQFP (DQ)
(2-chip enable version, 鈥淎鈥?indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
SA
BWa\
B W b\
BWc\
B W d\
CE2
CE\
SA
SA
81
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Organized 256K x 36
Fast Clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP package for high density, high speed
Low capacitive bus loading
OPTIONS
Timing
8.5ns/10ns/100MHz
10ns/15ns/66MHz
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Packages
100-pin TQFP (2-chip enable)
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Pinout
2-chip Enables
3-chip Enables
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Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
Industrial (-40
o
C to +85
o
C)
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MARKING
-8.5
-10
DQ No. 1001
A
(PRELIMINARY)
no indicator
XT
IT
DQPc
DQc
DQc
V
DD
Q
Vss
DQc
DQc
DQc
DQc
Vss
V
DD
Q
DQc
DQc
Vss
V
DD
NC
Vss
DQd
DQd
V
DD
Q
Vss
DQd
DQd
DQd
DQd
Vss
V
DD
Q
DQd
DQd
DQPd
1
2
3
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5
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DQPb
DQb
DQb
V
DD
Q
Vss
DQb
DQb
DQb
DQb
Vss
V
DD
Q
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
V
DD
CE2\
BWa\
BWb\
BWc\
BWd\
CE2
CE\
SA
SA
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SA
SA
SA
SA
SA
SA
SA
NF
NF
V
DD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x 36
SRAM core with advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK). The synchro-
nous inputs include all addresses, all data inputs, active LOW chip en-
able (CE\), two additional chip enables for easy depth expansion (CE2\,
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\). Note that CE2\ is not available on the
A version.
DQPc
DQc
DQc
V
DD
Q
Vss
DQc
DQc
DQc
DQc
Vss
V
DD
Q
DQc
DQc
Vss
V
DD
NC
Vss
DQd
DQd
V
DD
Q
Vss
DQd
DQd
DQd
DQd
Vss
V
DD
Q
DQd
DQd
DQPd
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80
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63
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59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
V
DD
Q
Vss
DQb
DQb
DQb
DQb
Vss
V
DD
Q
DQb
DQb
Vss
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
Vss
DQa
DQa
DQa
DQa
Vss
V
DD
Q
DQa
DQa
DQPa
50
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For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5SS256K36 &
AS5SS256K36A
Rev. 3.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SA
SA
SA
SA
SA
SA
SA
SA
NF
V
DD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
1

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