SSRAM
Austin Semiconductor, Inc.
256K x 18 SSRAM
Synchronous Burst SRAM,
Flow-Through
FEATURES
鈥?Fast access times: 8, 10, and 15ns
鈥?Fast clock speed: 113, 100, and 66 MHz
鈥?Fast clock and OE\ access times
鈥?Single +3.3V +0.3V/-0.165V power supply (V
DD
)
鈥?SNOOZE MODE for reduced-power standby
鈥?Common data inputs and data outputs
鈥?Individual BYTE WRTIE control and GLOBAL WRITE
鈥?Three chip enables for simple depth expansion and address
pipelining
鈥?Clock-controlled and registered addresses, data I/Os and
control signals
鈥?Interally self-timed WRITE cycle
鈥?Burst control pin (interleaved or linear burst)
鈥?Automatic power-down
鈥?Low capacitive bus loading
鈥?Operating Temperature Ranges:
- Military -55
o
C to +125
o
C
- Industrial -40
o
C to +85
o
C
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
AS5SS256K18
PIN ASSIGNMENT
(Top View)
100-pin TQFP
SA
SA
CE\
CE2
NC
NC
bwB\
BWa\
CE2\
V
DD
V
SS
CLK
GW\
BWE\
OE\
ADSC\
ADSP\
ADV\
SA
SA
OPTIONS
鈥?Timing
7.5ns/8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
鈥?Packages
100-pin TQFP
鈥?Operating Temperature Ranges:
- Military -55
o
C to +125
o
C
- Industrial -45
o
C to +85
o
C
*available as IT only.
MARKING
-8*
-9
-10
DQ
IT
XT
No. 1001
1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
1
1
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
For more products and information
please visit our web site at
www.austinsemiconductor.com
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Synchronous Burst SRAM family
employs high-speed, low power CMOS designs that are fabricated us-
ing an advanced CMOS process.
ASI鈥檚 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM
core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE\), two additional chip enables for easy depth expansion (CE2\,
AS5SS256K18
Rev. 2.0 12/00
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\).
Asynchronous inputs include the output enable (OE\), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE) that
selects between interleaved and linear burst modes. The data-out (Q),
enabled by OE\, is also asynchronous. WRITE cycles can be from one
to two bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status processor
(ADSP\) or address status controller (ADSC\) inputs. Subsequent burst
addresses can be internally generated as controlled by the burst ad-
vance input (ADV\).
Address and write control are registered on-chip to simplify WRITE
cycles. This allows self-timed WRITE cycles. Individual byte enables
allow individual bytes to be written. During WRITE cycles on this x18
device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins
and DQPb. GW\ LOW causes all bytes to be written. Parity bits are
available on this device.
ASI鈥檚 4Mb Synchronous Burst SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are TTL-compatible. The de-
vice is ideally suited for 486, Pentium廬, and PowerPC systems and
those systems that benefit from a wide synchronous data bus.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
MODE
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
NF**
NF**
SA
SA
SA
SA
SA
SA
SA
1
2
3
4
5
6
7
8
9
10
11
12
13
