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AS4SD16M16 Datasheet

  • AS4SD16M16

  • 256000Kbits 16M x 16 Replacement with DSCC 5962-n/a | SDRAM

  • 51頁

  • ETC

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SDRAM
Austin Semiconductor, Inc.
256 MB: 16 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
鈥?Full Military temp (-55擄C to 125擄C) processing available
鈥?Configuration: 16 Meg x 16 (4 Meg x 16 x 4 banks)
鈥?Fully synchronous; all signals registered on positive
edge of system clock
鈥?Internal pipelined operation; column address can be
changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8 or full page
鈥?Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
鈥?Self Refresh Mode (IT)
鈥?64ms, 8,192-cycle refresh (IT)
鈥?<24ms 8,192 cycle recfresh (XT)
鈥?WRITE Recovery (t
WR
= 鈥? CLK鈥?
鈥?LVTTL-compatible inputs and outputs
鈥?Single +3.3V 鹵0.3V power supply
AS4SD16M16
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
OPTIONS
鈥?/div>
Plastic Package - OCPL*
54-pin TSOP (400 mil)
Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or
7.5ns @ CL = 2 (PC100)
MARKING
DG
No. 901
鈥?/div>
-75
鈥?/div>
Operating Temperature Ranges
-Industrial Temp (-40擄C to 85擄 C)
IT
-Industrial Plus Temp
(-45擄C to +105擄C)
IT+
-Military Temp (-55擄C to 125擄C)
XT***
16 Meg x 16
Configuration
4 Meg x 16 x 4 banks
Refresh Count
8K
Row Addressing
8K (A0-A12)
Bank Addressing
4 (BA0, BA1)
Column Addressing
512 (A0-A8)
Note: 鈥淺鈥?indicates an active low.
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
GRADE FREQUENCY CL = 2** CL = 3**
-75
133 MHz
鈥?/div>
5.4ns
-75
100 MHz
6ns
鈥?/div>
*Off-center parting line
**CL = CAS (READ) latency
***Consult Factory
SETUP
TIME
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4SD16M16
Rev. 1.5 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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