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AS4LC4M4 Datasheet

  • AS4LC4M4

  • 16384Kbits 4M x 4 Replacement with DSCC 5962-n/a | DRAM

  • 20頁

  • ETC

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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
DRAM
AVAILABLE IN MILITARY
SPECIFICATIONS
鈥?MIL-STD-883
鈥?SMD Planned
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
PIN ASSIGNMENT (Top View)
24/28-Pin
1
1
2
2
3
3
4
4
5
5
6
6
9
8
10
9
11
10
12
11
13
12
14
13
28
26
27
25
26
24
25
23
24
22
23
21
20
19
19
18
18
17
17
16
16
15
15
14
V
SS
DQ4
DQ3
/
C
/
A
/
S
/
O
/
E
A9
A8
A7
A6
A5
A4
Vss
FEATURES
鈥?Industry-standard x4 pinout, timing, functions and
packages
鈥?High-performance CMOS silicon-gate process
鈥?Single +3.3V
鹵0.3V
power supply
鈥?Low power, 1mW standby; 150mW active, typical
鈥?All inputs, outputs and clocks are TTL-compatible
鈥?Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR)
HIDDEN
鈥?2,048-cycle (11 row-, 11 column-addresses)
鈥?Extended Data-Out (EDO) PAGE access cycle
鈥?5V-tolerant I/Os (5.5V maximum V
IH
level)
V
CC
DQ1
DQ2
/
W
/
E
/
R
/
A
/
S
NC
A10
A0
A1
A2
A3
V
CC
OPTIONS
鈥?Timing
60ns access (Contact Factory)
70ns acess
80ns access
鈥?Packages
Ceramic SOJ
Ceramic LCC
Ceramic Gull Wing
MARKING
-6
-7
-8
ECJ
EC
ECG
No. 505
No. 212
No. 603
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
110ns
130ns
150ns
60ns
70ns
80ns
30ns
35ns
40ns
30ns
35ns
40ns
15ns
18ns
20ns
12ns
15ns
20ns
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. The AS4LC4M4
?
R
?
A
/
S is used to latch the first 11
bits and
?
C
?
A
/
S the latter 11 bits. READ and WRITE cycles are
selected with the
?
W
/
E input. A logic HIGH on
?
W
/
E dictates READ mode while a logic LOW on
?
W
/
E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of
?
W
/
E or
?
C
?
A
/
S, whichever occurs last. If
?
W
/
E goes LOW prior to
?
C
?
A
/
S going LOW, the output pins
remain open (High- Z) until the next
?
C
?
A
/
S cycle, regardless
of
?
O
/
E.
AS4LC4M4
Rev. 11/97
DS000022
A logic HIGH on
?
W
/
E dictates READ mode while a logic
LOW on
?
W
/
E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of
?
W
/
E or
/
C
/
A
/
S,
whichever occurs last. An EARLY WRITE occurs when
?
W
/
E is taken LOW prior to
/
C
/
A
/
S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when
?
W
/
E falls after
/
C
/
A
/
S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
OE. During LATE WRITE or READ-MODIFY-WRITE cycles,
? /
?
O
/
E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping
?
O
/
E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by
?
W
/
E and
?
O
/
E.
FAST PAGE MODE
FAST PAGE operations allow faster data operations
(READ, WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by
?
R
?
A
/
S
followed by a column-address strobed-in by C
?
A
/
S.
?
C
?
A
/
S may
?
be toggled-in by holding
?
R
?
A
/
S LOW and strobing-in differ-
ent column-addresses, thus executing faster memory cycles.
Returning R?A
/
S HIGH terminates the FAST PAGE MODE
of operation.
2-73
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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