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DRAM

Austin Semiconductor, Inc.

4 MEG x 16 DRAM

Extended Data Out (EDO) DRAM

FEATURES

鈥?Single +3.3V 鹵0.3V power supply.

鈥?Industry-standard x16 pinout, timing, functions, and

package.

鈥?12 row, 10 column addresses

鈥?High-performance CMOS silicon-gate process

鈥?All inputs, outputs and clocks are LVTTL-compatible

鈥?Extended Data-Out (EDO) PAGE MODE access

鈥?4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH

distributed across 64ms

鈥?Optional self refresh (S) for low-power data retention

鈥?Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020

AS4LC4M16

PIN ASSIGNMENT

(Top View)

50-Pin TSOP (DG)

OPTIONS

鈥?Package(s)

50-pin TSOP (400-mil)

鈥?Timing

50ns access

60ns access

鈥?Refresh Rates

Standard Refresh

Self Refresh

鈥?Operating Temperature Ranges

Military (-55擄C to +125擄C)

Industrial (-40擄C to +85擄C)

MARKINGS

DG

-5

-6

Configuration

Refresh

Row Address

Column Addressing

4 Meg x 16

4K

A0-A11

A0-A9

None

S*

XT

IT

NOTE:

The \ symbol indicates signal is active LOW.

*Contact factory for availability. Self refresh option available on IT

version only.

KEY TIMING PARAMETERS

t

RAC

SPEED t

RC

-5

84ns 50ns

-6

104ns 60ns

t

PC

20ns

25ns

t

AA

25ns

30ns

t

CAC

13ns

15ns

t

CAS

8ns

10ns

For more products and information

please visit our web site at

www.austinsemiconductor.com

AS4LC4M16

Rev. 1.0 7/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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