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AS4LC1M16883C Datasheet

  • AS4LC1M16883C

  • 1 MEG x 16 DRAM

  • 194.65KB

  • 22頁

  • ETC

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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
鈥?MIL-STD 883
鈥?SMD Planned
1 MEG x 16 DRAM
3.3V, EDO PAGE MODE,
OPTIONAL EXTENDED REFRESH
PIN ASSIGNMENT (Top View)
44/50-Pin SOJ/LCC/Gull Wing
450mil
FEATURES
鈥?JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
鈥?High-performance CMOS silicon-gate process
鈥?Single +3.3V
鹵0.3V
power supply
鈥?All device pins are TTL-compatible
鈥?Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR),
HIDDEN
鈥?BYTE WRITE access cycles
鈥?1,024-cycle refresh (10 row-, 10 column-addresses)
鈥?Low power, 0.3mW standby; 180mW active, typical
鈥?Extended Data-Out (EDO) PAGE access cycle
鈥?5V-tolerant I/Os (5.5V maximum V
IH
level)
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
OPTIONS
鈥?Timing
60ns access (Contact Factory)
70ns access
80ns access
鈥?Refresh Rate
Standard 16ms period
鈥?Packages
Ceramic SOJ
Ceramic Gull Wing
Ceramic LCC
MARKING
-6
-7
-8
None
ECJ No. 506
ECG No. 604
EC No. 213
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
Vcc
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL
CASH
OE
A9
A8
A7
A6
A5
A4
Vss
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
150ns
60ns
70ns
80ns
25ns
30ns
40ns
30ns
35ns
40ns
15ns
20ns
20ns
12ns
12ns
20ns
GENERAL DESCRIPTION
The AS4LC1M16 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 con-
figuration. The AS4LC1M16 has both BYTE WRITE and
WORD WRITE access cycles via two
?
C
?
A
/
S pins (?C
?
A
?
S
/
L and
?
C
?
A
?
S
?
H). These function in a similar manner to a single
?
C
?
AS
of other DRAMs in that either
?
C
?
A
?
S
/
L or C
?
A
?
S
?
H will generate
?
AS4LC1M16
REV. 3/97
DS000020
an internal
?
C
?
A
/
S.
The AS4LC1M16
?
C
?
A
/
S function and timing are deter-
mined by the first
?
C
?
A
/
S (?C
?
A
?
S
/
L or
?
C
?
A
?
S
?
H) to transition LOW
and the last
?
C
?
A
/
S to transition back HIGH. Use of only one
of the two results in a BYTE WRITE cycle.
?
CASL transitioning
? ? /
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and
?
C
?
A
?
S
?
H transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
Each bit is uniquely addressed through the 20 address bits
during READ or WRITE cycles. These are entered 10 bits
(A0 -A9) at a time.
?
R
?
A
/
S is used to latch the first 10 bits and
?
C
?
A
/
S the latter 10 bits. The
?
C
?
A
/
S function also determines
whether the cycle will be a refresh cycle (?R
?
A
/
S ONLY) or an
active cycle (READ, WRITE or READ WRITE) once
?
R
?
A
/
S
goes LOW.
2-93
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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