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AM28F256A Datasheet

  • AM28F256A

  • Advanced Micro Devices [256 Kilobit (32 K x 8-Bit) CMOS 12....

  • AMD

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FINAL
Am28F256A
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s
High performance
鈥?Access times as fast as 70 ns
s
CMOS low power consumption
鈥?30 mA maximum active current
鈥?100 碌A(chǔ) maximum standby current
鈥?No data retention power consumption
s
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
鈥?32-pin PDIP
鈥?32-pin PLCC
鈥?32-pin TSOP
s
100,000 write/erase cycles minimum
s
Write and erase voltage 12.0 V
鹵5%
s
Latch-up protected to 100 mA from 鈥? V to
V
CC
+1 V
s
Embedded Erase Electrical Bulk Chip-Erase
鈥?1.5 seconds typical chip-erase including
pre-programming
s
Embedded Program
鈥?14 碌s typical byte-program including time-out
鈥?0.5 second typical chip program
s
Command register architecture for
microprocessor/microcontroller compatible
write interface
s
On-chip address and data latches
s
Advanced CMOS flash memory technology
鈥?Low cost single transistor memory cell
s
Embedded algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F256A is a 256 K Flash memory organized
as 32 Kbytes of 8 bits each. AMD鈥檚 Flash memories
offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F256A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in standard EPROM programmers. The
Am28F256A is erased when shipped from the factory.
The standard Am28F256A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F256A has separate chip enable (CE#)
and output enable (OE#) controls.
AMD鈥檚 Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.
AMD鈥檚 Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
Publication#
18879
Rev:
C
Amendment/+2
Issue Date:
May 1998
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
nal electr ic fields for erase a nd programmi ng
operations produces reliable cycling. The Am28F256A
uses a 12.0V鹵 5% V
PP
high voltage input to perform
the erase and programming functions.
The highest degree of latch-up protection is achieved
with AMD鈥檚 proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from 鈥? V to V
CC
+1 V.
Embedded Program
The Am28F256A is byte programmable using the
Embedded Programming algorithm. The Embedded
Programming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F256A is one half second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are

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AM28F256A-70EE,AM28F256A-70EI,AM28F256A-70FE,AM28F256A-70FI,AM28F256A-70PI

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