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ADM4850 Datasheet

  • ADM4850

  • 5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Tr...

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5 V Slew-Rate Limited Half- and Full-Duplex
RS-485/RS-422 Transceivers
ADM4850鈥揂DM4857
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854鈥?15 kbps
ADM4851/ADM4855鈥?00 kbps
ADM4852/ADM4856鈥?.5 Mbps
ADM4853/ADM4857鈥?0 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 碌A (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-z when disabled or powered off
鈭? V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with MAX308x
Specified over the 鈭?0擄C to +85擄C temperature range
Available in 8-lead SOIC and LFCSP packages
FUNCTIONAL BLOCK DIAGRAM
V
CC
V
CC
ADM4850/ADM4851/
ADM4852/ADM4853
RO
RE
DE
DI
D
R
A
B
DI
RO
ADM4854/ADM4855/
ADM4856/ADM4857
A
R
B
Z
D
Y
04931-001
GND
GND
Figure 1.
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
GENERAL DESCRIPTION
The ADM4850鈭扐DM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication
on multipoint bus transmission lines. They are designed for
balanced data transmission and comply with EIA Standards
RS-485 and RS-422. The ADM4850鈭扐DM4853 are half-duplex
transceivers, which share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854鈭扐DM4857 transceivers have dedicated differential
line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Since only one driver
should be enabled at any time, the output of a disabled or pow-
ered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures a
logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges, and are available in 8-lead SOIC and LFCSP
packages.
Table 1. Selection Table
Part No
ADM4850
ADM4851
ADM4852
ADM4853
ADM4854
ADM4855
ADM4856
ADM4857
Half-/Full-Duplex
Half
Half
Half
Half
Full
Full
Full
Full
Data Rate
115 kbps
500 kbps
2.5 Mbps
10 Mbps
115 kbp
500 kbps
2.5 Mbps
10 Mbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
漏 2004 Analog Devices, Inc. All rights reserved.

ADM4850 PDF文件相關型號

ADM4852,ADM4853,ADM4854,ADM4855,ADM4856,ADM4857

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