4 Channel 500MSPS DDS with 10-bit DACs
Preliminary Technical Data
FEATURES
Four synchronized DDS channels @500 MSPS
Independent frequency / phase / amplitude
control between all channels
Matched latencies for Freq, Phase, and Amplitude changes
Excellent channel to channel isolation
Frequency sweeping capability
Up to 16 levels of modulation (pin selectable)
Individually programmable DAC full scale currents
Four integrated 10-bit D/A converters(DACs)
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude scaling resolution
Serial I/O Port(SPI) with enhanced data throughput
AD9959
Software/Hardware controlled power-down
Dual supply operation (1.8 V DDS core / 3.3 V serial I/O)
Built-in synchronization for multiple devices
Selectable REF_CLK multipier(PLL) 4x to 20x (bypassable)
Selectable REF_CLK crystal operation
56 pin LFCSP package
APPLICATIONS
Agile L.O. frequency synthesis
Phased array radar / sonar
Instrumentation
Synchronized clocking
RF source for AOTF
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
FREQUENCY
ACCUMULATOR
32
危
32
危
危
15
COS(X)
10
脳
脳
脳
脳
10
10
DAC
IOUT
IOUT
DDS CORE
FREQUENCY
ACCUMULATOR
32
危
32
危
危
15
COS(X)
10
10
DAC
IOUT
IOUT
DDS CORE
FREQUENCY
ACCUMULATOR
32
危
32
危
危
15
COS(X)
10
10
DAC
IOUT
IOUT
DDS CORE
FREQUENCY
ACCUMULATOR
RAMP
RATE
DFTW
SYNC_IN
SYNC_OUT
I/O_UPDATE
32
危
32
危
危
15
COS(X)
10
10
DAC
IOUT
IOUT
DAC_RSET
32
8
FTW
32
PHASE
OFFSET
14
DIGITAL
MULTIPLIER
SCALABLE
DAC REF
CURRENT
Timing & Control Logic
SYSTEM
CLK
CONTROL
REGISTERS
PWR_DWN_CTL
MASTER_RESET
SYNC_CLK
梅4
SCLK
CS
OSC / REF_CLK
OSC / REF_CLK
BUFFER / XTAL
OSCILLATOR
REF CLOCK
MULTIPLIER
(PLL) 4x to 20x
M
U
X
CHANNEL
REGISTERS
PROFILE
REGISTERS
I/O
Port
Buffer
SDIO_0
SDIO_1
SDIO_2
SDIO_3
1.8V
AVDD
CLK_MODE_SEL
1.8V
DVDD
P P P P
S S S S
0 1 2 3
3.3V
DVDD_IO
Figure 1 AD9959 Block Diagram
Rev. PrB
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Specifications subject to change without notice. No license is granted by implication
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