Preliminary Technical Data
FEATURES
40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA
Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 脳 V
REF
(20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, Independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal Monitor Function
DSP/microcontroller-compatible serial interface
LVDS serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
DV
CC
V
DD
V
SS
AGND DNGD
40-Channel, 14-Bit
Serial Input, Voltage-Output DAC
AD5371
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
LDAC
VREF0
CONTROL
REGISTER
14
14
8
14
14
14
14
SPI/LVDS
SYNC
SDI
SCLK
SYNC
SDI
SCLK
SDO
BUSY
8
RESET
CLR
STATE
MACHINE
14
14
14
14
14
A/B SELECT
REGISTER
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
8
MUX
1
14
14
14
TO
MUX 2's
14
X2A REGISTER
X2B REGISTER
MUX 14
2
14
OFS1 14
REGISTER
DAC 0 14
REGISTER
OFFSET
DAC 1
BUFFER
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
SERIAL
INTERFACE
14
14
14
14
A/B SELECT
REGISTER
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
8
MUX
1
14
14
14
TO
MUX 2's
14
X2A REGISTER
X2B REGISTER
MUX 14
2
14
OFS0
REGISTER
DAC 0 14
REGISTER
OFFSET
DAC 0
BUFFER
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
BUFFER
GROUP 0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
路
路
路
路
路
路
路
路
路
路
路
路
MUX
1
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
14
14
路
路
路
路
路
路
14
路
路
路
路
路
路
14
路
路
路
路
路
路
X2A REGISTER
X2B REGISTER
MUX 14
2
路
路
路
路
路
路
DAC 7 14
REGISTER
路
路
路
路
路
路
路
路
路
路
路
路
DAC 7
路
路
路
路
路
路
OUTPUT BUFFER
AND POWER
DOWN CONTROL
GROUP 1
VREF1
POWER-ON
RESET
14
14
14
14
路
路
路
路
路
路
路
路
路
路
路
路
MUX
1
X1A REGISTER
X1B REGISTER
M REGISTER
C REGISTER
14
14
路
路
路
路
路
路
14
路
路
路
路
路
路
14
路
路
路
路
路
路
路
路
路
路
路
路
MUX 14
2
X2A REGISTER
X2B REGISTER
DAC 7 14
REGISTER
路
路
路
路
路
路
路
路
路
路
路
路
DAC 7
路
路
路
路
路
路
OUTPUT BUFFER
AND POWER
DOWN CONTROL
AD5371
GROUPS 2 TO 4
SAME AS GROUP 1
VREF2 SUPPLIES
GROUPS 2 TO 4
VREF2
VOUT16
TO
VOUT39
5371-0001
SIGGND2
SIGGND3
SIGGND4
Figure 1.
AD5371鈥擯rotected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
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