a
FEATURES
500 MHz Driver Operation (1 Gb/s)
Driver Inhibit Function
100 ps Edge Matching
Guaranteed Industry Specifications
20 Output Impedance
5 V/ns Slew Rate
Variable Output Voltages for ECL, TTL, and CMOS
High-Speed Differential Inputs for Maximum Flexibility
Ultrasmall 100-Lead LQFP Package with Built-In
Heat Sink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
Quad Ultrahigh-Speed Pin Driver
with High-Z and V
TERM
Modes
AD53513
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC1
VCC2
VEE
VCC3
VCC4
VEE3
VEE1
VEE2
VEE4
RLD1
VBB
VH1
DATA1
DATAB1
INH1
INHB1
VL1
VT1
VH2
DATA2
DATAB2
INH2
INHB2
VL2
VT2
VBB
RLD2
RLD3
VBB
VH3
DATA3
DATAB3
INH3
INHB3
VL3
VT3
VH4
DATA4
DATAB4
INH4
INHB4
VL4
VT4
VBB
RLD4
GND
VHDCPL1 39nF
20
ROUT
VOUT1
VLDCPL1
30
39nF
50
DRIVER 1
VHDCPL2 39nF
20
ROUT
VOUT2
VLDCPL2
30
39nF
50
DRIVER 2
PRODUCT DESCRIPTION
AD53513
VHDCPL3 39nF
20
ROUT
VOUT3
VLDCPL3
30
39nF
50
The AD53513 is a quad high-speed pin driver designed for use
in digital or mixed-signal test systems. Combining a high-speed
monolithic process with a convenient surface-mount package,
this product attains superb electrical performance while preserving
optimum packaging densities and long-term reliability in a
100-lead, LQFP package with built-in heat sink.
Featuring unity gain programmable output levels of 鈥?.5 V to
+5.5 V, with output swing capability of less than 200 mV to
8 V, the AD53513 is designed to stimulate ECL, TTL, and
CMOS logic families, as well as high-speed memory. The
1.0 Gb/s data rate capacity and matched output impedance
allow for real-time stimulation of these digital logic families.
To test I/O devices, the pin driver can be switched into a high
impedance state (Inhibit Mode), electrically removing the driver
from the path. The pin driver leakage current in inhibit is typically
100 nA and output charge transfer entering inhibit is typically less
than 20 pC.
The AD53513 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high-speed differential inputs with a common-mode range of
鹵
2 V. This allows for direct interface to precision differential
ECL timing. The analog logic HI/LO inputs are equally easy
to interface. Typically requiring 10
碌A(chǔ)
of bias current, the
AD53513 can be directly coupled to the output of a digital-
to-analog converter.
Each channel of the AD53513 has a Mode Select Pin RLD,
which is a single-sided logic input. The logic threshold is set by
DRIVER 3
VHDCPL4 39nF
20
ROUT
VOUT4
VLDCPL4
30
39nF
50
DRIVER 4
TVCC
GND
GND
GND
GND
1.0 A/K
THERM
the VBB input which is common to all four channels. The RLD
Mode Select controls whether inhibit puts the driver in High-Z
or V
TERM
mode. (Refer to Table I.) All of the digital logic inputs
(DATA, DATAB, INH, INHB, RLD, VBB), must share a
common set of logic levels. The VBB threshold should be set to
the midrange of the logic levels. For example, if ECL levels of
鈥?.8 V to 鈥?.8 V are used, VBB should be set to 鈥?.3 V.
The AD53513 is available in a 100-lead, LQFP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of 鈥?5擄C to +85擄C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2002
1
2
3
4
