鈩?/div>
or other complex impedance load
requirements. Without a backmatch resistor it is also capable of
driving highly capacitive loads, typically achieving a rise/fall time
of less than 10 ns with a 1000 pF capacitance. To test I/O
devices, the pin driver can be switched into a high impedance
state (Inhibit Mode), electrically removing the driver from the
path. The pin driver leakage current in inhibit is typically less
than 1
碌A
and output capacitance is typically less than 18 pF.
Transitions from HI/LO or to inhibit are controlled through the
data and inhibit inputs. The input circuitry utilizes high-speed
differential inputs with a common-mode range of 鈥? V to +5 V.
This allows for direct interface to the precision of differential
ECL timing or the simplicity of stimulating the pin driver from a
single-ended CMOS or TTL logic source or any combination
over the common-mode range. The analog logic HI/LO inputs
are equally easy to interface, typically requiring 50
碌A
of bias
current.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 1999
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