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AD5314BRM Datasheet

  • AD5314BRM

  • 2.5 V to 5.5 V, 500 uA, Quad Voltage Output 8-/10-/12-Bit DA...

  • 15頁

  • AD

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a
2.5 V to 5.5 V, 500 A, Quad Voltage Output
8-/10-/12-Bit DACs in 10-Lead microSOIC
AD5304/AD5314/AD5324*
GENERAL DESCRIPTION
FEATURES
AD5304
Four Buffered 8-Bit DACs in 10-Lead microSOIC
AD5314
Four Buffered 10-Bit DACs in 10-Lead microSOIC
AD5324
Four Buffered 12-Bit DACs in 10-Lead microSOIC
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0鈥揤
REF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Low Power, SPI鈩? QSPI鈩? MICROWIRE鈩? and
DSP-Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Ampli鏗乪rs
Temperature Range 鈥?0 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500
碌A
at 3 V. Their on-chip output ampli鏗乪rs allow rail-to-
rail output swing to be achieved with a slew rate of 0.7 V/碌s.
A 3-wire serial interface is used which operates at clock rates
up to 30 MHz and is compatible with standard SPI, QSPI,
MICROWIRE and DSP interface standards.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software
LDAC
function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. The parts contain a power-down feature that
reduces the current consumption of the device to 200 nA @ 5 V
(80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1
碌W
in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
V
DD
LDAC
REFIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
V
OUT
A
SCLK
SYNC
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
V
OUT
D
POWER-ON
RESET
AD5304/AD5314/AD5324
GND
POWER-DOWN
LOGIC
*Protected
by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2000

AD5314BRM 產(chǎn)品屬性

  • Data Converter FundamentalsDAC Architectures

  • 50

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • -

  • 7µs

  • 10

  • 串行

  • 4

  • 單電源

  • 5mW

  • -40°C ~ 105°C

  • 表面貼裝

  • 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）

  • 10-MSOP

  • 管件

  • 4 電壓，單極；4 電壓，雙極

  • 143k

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