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AD5312BRM Datasheet

  • AD5312BRM

  • +2.5 V to +5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8...

  • 16頁(yè)

  • AD

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a
+2.5 V to +5.5 V, 230 A Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs
AD5302/AD5312/AD5322*
GENERAL DESCRIPTION
FEATURES
AD5302: Two 8-Bit Buffered DACs in One Package
AD5312: Two 10-Bit Buffered DACs in One Package
AD5322: Two 12-Bit Buffered DACs in One Package
10-Lead SOIC Package
Micropower Operation: 300 A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
0鈥揤
REF
Output Voltage
Power-On-Reset to Zero Volts
Simultaneous Update of DAC Outputs via
LDAC
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
The AD5302/AD5312/AD5322 are dual 8-, 10- and 12-bit buff-
ered voltage output DACs in a 10-lead
碌SOIC
package that
operate from a single +2.5 V to +5.5 V supply consuming
230
碌A(chǔ)
at 3 V. Their on-chip output amplifiers allow the outputs
to swing rail-to-rail with a slew rate of 0.7 V/碌s. The AD5302/
AD5312/AD5322 utilize a versatile 3-wire serial interface which
operates at clock rates up to 30 MHz and is compatible with
standard SPI鈩? QSPI鈩? MICROWIRE鈩?and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs may be configured as
buffered or unbuffered inputs. The outputs of both DACs may
be updated simultaneously using the asynchronous
LDAC
in-
put. The parts incorporate a power-on-reset circuit that ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a power-
down feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides software-
selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip-
ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1
碌W
in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
V
DD
POWER-ON
RESET
V
REF
A
AD5302/AD5312/AD5322
INPUT
REGISTER
SYNC
INTERFACE
LOGIC
SCLK
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
BUFFER
V
OUT
A
POWER-DOWN
LOGIC
RESISTOR
NETWORK
DAC
REGISTER
STRING
DAC
BUFFER
V
OUT
B
RESISTOR
NETWORK
LDAC
V
REF
B
GND
*Patent Pending; protected by U.S. Patent No. 5684481.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 1999

AD5312BRM 產(chǎn)品屬性

  • Data Converter FundamentalsDAC Architectures

  • 50

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • -

  • 6µs

  • 10

  • 串行

  • 2

  • 單電源

  • 2.5mW

  • -40°C ~ 105°C

  • 表面貼裝

  • 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）

  • 10-MSOP

  • 管件

  • 2 電壓，單極；2 電壓，雙極

  • 143k

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