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AD5307BRU Datasheet

  • AD5307BRU

  • IC-SM-QUAD 8-BIT DAC 2.5V

  • 235.94KB

  • 20頁(yè)

  • ETC

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a
2.5 V to 5.5 V, 400 A, Quad Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5307/AD5317/AD5327*
GENERAL DESCRIPTION
FEATURES
AD5307: Four Buffered 8-Bit DACs in 16-Lead TSSOP
AD5317: Four Buffered 10-Bit DACs in 16-Lead TSSOP
AD5327: Four Buffered 12-Bit DACs in 16-Lead TSSOP
Low Power Operation: 400 A @ 3 V, 500 A @ 5 V
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0鈥揤
REF
or 0鈥? V
REF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Pin)
Asynchronous Clear Facility (CLR Pin)
Low Power, SPI鈩? QSPI鈩? MICROWIRE鈩?and DSP-
Compatible 3-Wire Serial Interface
SDO Daisy-Chaining Option
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range 鈥?0 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
The AD5307/AD5317/AD5327 are quad 8-, 10-, and 12-bit
buffered voltage-output DACs, in a 16-lead TSSOP package,
which operate from a single 2.5 V to 5.5 V supply consuming
400
碌A(chǔ)
at 3 V. Their on-chip output amplifiers allow the outputs
to swing rail-to-rail with a slew rate of 0.7 V/碌s. The AD5307/
AD5317/AD5327 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with stan-
dard SPI, QSPI, MICROWIRE, and DSP interface standards.
The references for the four DACs are derived from two refer-
ence pins (one per DAC pair). These reference inputs can be
configured as buffered or unbuffered inputs. The parts incorpo-
rate a power-on-reset circuit that ensures that the DAC outputs
power-up to 0 V and remain there until a valid write to the device
takes place. There is also an asynchronous active-low
CLR
pin
that clears all DACs to 0 V. The outputs of all DACs may be
updated simultaneously using the asynchronous
LDAC
input.
The parts contain a power-down feature that reduces the current
consumption of the devices to 300 nA @ 5 V (90 nA @ 3 V).
The parts may also be used in daisy-chaining applications using
the SDO pin.
All three parts are offered in the same pinout, which allows
users to select the amount of resolution appropriate for their
application without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
REF
AB
GAIN-SELECT
LOGIC
DAC
REGISTER
STRING
DAC A
AD5307/AD5317/AD5327
LDAC
INPUT
REGISTER
BUFFER
V
OUT
A
SCLK
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
SYNC
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
INPUT
REGISTER
SDO
DAC
REGISTER
STRING
DAC D
BUFFER
POWER-DOWN
LOGIC
V
OUT
D
POWER-ON
RESET
DCEN
LDAC CLR
V
REF
CD
PD
GND
*Protected
by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2000

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