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AD1892 Datasheet

  • AD1892

  • Integrated Digital Receiver/Rate Converter

  • 24頁

  • AD

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a
FEATURES
Complete EIAJ CP-340 (CP-1201), IEC-958, AES/EBU,
S/PDIF Compatible Digital Audio Receiver and
Asynchronous Sample Rate Converter
Status Pins and Microprocessor Interfaces for
Stand-Alone and Microcontroller-Oriented Operation
Integrated Channel Status Buffer and Q-Channel
Subcode Buffer (Supports EIAJ CP-2401)
20-Bit SamplePort
廬
Architecture Provides Superb Jitter
Rejection on Input Port
Sample Rate Conversion from 8 kHz to 48 kHz with
1:5 Upsampling Range
1:0.85 Downsampling Range
120 dB Dynamic Range
鈥?13 dB THD+N @ 1 kHz
CRC Calculation on Q-Channel Subcode (Consumer
Mode Only) and on Channel Status (Pro Mode Only)
Four-Wire SPI鈩?Compatible Serial Control Port
Mute Input Pin
Power-Down Mode
Single +5 V Supply
Flexible Three-Wire Serial Data Port with Left-Justified,
Right-Justified and I
2
S-Compatible Modes
28-Lead SOIC Package
APPLICATIONS
DVD, DAT, MD, DCC and CD-R Recorders and Players
Computer Multimedia Products
DAB Receivers, Automotive Digital Audio Networks
Integrated Digital
Receiver/Rate Converter
AD1892
PRODUCT OVERVIEW
The AD1892 combines a CP-1201, CP-340, IEC-958, AES/
EBU, S/PDIF compatible Digital Audio Receiver (DAR) with
an asynchronous sample rate converter, allowing the user to
specify the output sample rate of the received digital audio infor-
mation. The DAR block features support for both Q-channel
subcode information (to support CD, CD-R, MD and DAT
digital audio formats) as well as Channel Status information. A
microcontroller interface, with an SPI compatible serial port,
allows full access to the 80-bit Q-Channel subcode buffer and to
the 32-bit Channel Status buffer, as well as to the control and
status registers. Additionally, key status information from the
incoming subframes and the Channel Status buffer is reported
on status output pins on the AD1892, so the AD1892 may be
used in systems that do not include a microcontroller or
microprocessor.
The asynchronous sample rate converter block is based on
market leading AD1890 family SamplePort rate conversion tech-
nology. The AD1892 offers a 1:5 upsampling range, and will
downsample from 48 kHz to 44.1 kHz. Input audio word widths
up to 20 bits are supported, and output audio word widths of 16
or 20 are supported, with 120 dB of dynamic range and 鈥?13 dB
THD+N. The rate converter inherently rejects jitter on the
recovered clocks from the incoming biphase-mark encoded
stream. Indeed, sample rate conversion is highly synergistic
with digital audio reception, allowing the use of a fully digital
phase locked loop clock recovery scheme with highly robust
clock recovery and jitter rejection.
(continued
on Page 4)
FUNCTIONAL BLOCK DIAGRAM
512 x F
SOUT
POWER-DOWN/RESET
MUTE
CLOCK
GENERATOR
ASYNCH SAMPLE
RATE CONVERTER
DATA
OUTPUT SERIAL
INTERFACE
BYPASS
3
BCLK
LRCLK
SDATA
SYNC
CA
BIPHASE-MARK
2
INPUT
BIPHASE-MARK
RECEIVER
COMPARATOR
CONTROL
CRC
CHECK
Q-CHANNEL
SUBCODE BUFFER
CRC
CHECK
CHANNEL STATUS
BUFFER
CB
CC
CD
CE
CON/PRO
CSCLK
AD1892
MICROCONTROLLER
INTERFACE
4
NO
SIGNAL
ERROR
INTERRUPT U/C BIT
SFCLK
QDFS
CLOCK, LATCH,
DATA IN,
DATA OUT
2
DIGITAL
SUPPLY
SamplePort is a registered trademark of Analog Devices, Inc.
SPI is a trademark of Motorola, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 1998

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