TM
ACTS74MS
Radiation Hardened Dual D
Flip Flop with Set and Reset
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14,
LEAD FINISH C
TOP VIEW
R1 1
D1 2
CP1 3
S1 4
Q1 5
Q1 6
GND 7
14 VCC
13 R2
12 D2
11 CP2
10 S2
9 Q2
8 Q2
January 1996
Features
鈥?Devices QML Qualified in Accordance with MIL-PRFF-38535
itle
CTS
MS)
b-
t
adia-
n
rd-
ed
al D
p
p
th
t and
set)
thor
ey-
rds
ter-
mi-
n-
ctor,
dia-
n
rd-
ed,
,
d
rd,
L,
tel-
,
D,
ass
鈥?Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96713 and Intersil鈥檚 QM Plan
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity: <1 x
(Typ)
10
-10
Errors/Bit/Day
鈥?SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
鈥?Dose Rate Upset . . . . . . . . . . . . . . . .
鈥?Dose Rate Survivability . . . . . . . . . . .
>10
11
>10
12
RAD (Si)/s, 20ns Pulse
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
鈥?Significant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
鈥?Input Current
鈮?/div>
1碌A(chǔ) at VOL, VOH
鈥?Fast Propagation Delay . . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ)
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP3-F14,
LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
R2
D2
CP2
S2
Q2
Q2
Description
The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with
Set(s) and Reset (R). The logic level at data input is transferred to the
output during the positive transition of the clock. The Set and Reset are
independent from the clock and accomplished by a low level on the
appropriate input.
The ACTS74MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
14 Lead Ceramic Dual-In-Line Package (D suffix).
Q1
GND
Ordering Information
PART NUMBER
5962F9671301VCC
5962F9671301VXC
ACTS74D/Sample
ACTS74K/Sample
ACTS74HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2001, All Rights Reserved
1
Spec Number
File Number
518787
3382.1
INTERSIL
1
2
3
