SN74ACT7881
1024
脳
18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS227E 鈥?FEBRUARY 1993 鈥?REVISED APRIL 1998
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D
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Member of the Texas Instruments
Widebus鈩?Family
Independent Asynchronous Inputs and
Outputs
Read and Write Operations Can Be
Synchronized to Independent System
Clocks
Programmable Almost-Full/Almost-Empty
Flag
Pin-to-Pin Compatible With SN74ACT7882,
SN74ACT7884, and SN74ACT7811
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Input-Ready, Output-Ready, and Half-Full
Flags
Expandable in Word Width and/or Word
Depth
Fast Access Times of 11 ns With a 50-pF
Load
High Output Drive for Direct Bus Interface
Package Options Include 68-Pin Plastic
Leaded Chip Carrrier (FN) or 80-Pin Shrink
Quad Flat (PN) Package
FN PACKAGE
(TOP VIEW)
D14
D13
D12
D11
D10
D9
V
CC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
D15
D16
D17
GND
RDCLK
RDEN1
RDEN2
OE
RESET
V
CC
GND
OR
V
CC
Q17
Q16
GND
Q15
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
8 7
6
5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V
CC
Q14
Q13
GND
Q12
Q11
V
CC
Q10
Q9
GND
Q8
Q7
V
CC
Q6
Q5
GND
Q4
DAF
GND
WRTCLK
WRTEN1
WRTEN2
V
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
AF/AE
GND
IR
HF
V
CC
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
Q0
Q1
GND
Q2
Q3
V
CC
Copyright
漏
1998, Texas Instruments Incorporated
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