CD54ACT00, CD74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS308B 鈥?JANUARY 2001 鈥?REVISED JUNE 2002
D
D
D
D
D
D
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
鹵24-mA
Output Drive Current
鈥?Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54ACT00 . . . F PACKAGE
CD74ACT00 . . . E OR M PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
description
The 鈥楢CT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A
S
B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PACKAGE鈥?/div>
PDIP 鈥?E
鈥?5擄C to 125擄C
55擄C
SOIC 鈥?M
CDIP 鈥?F
Tube
Tube
Tape and reel
Tube
ORDERABLE
PART NUMBER
CD74ACT00E
CD74ACT00M
CD74ACT00M96
CD54ACT00F3A
TOP-SIDE
MARKING
CD74ACT00E
ACT00M
CD54ACT00F3A
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
錚?/div>
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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