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ACS8522 Datasheet

  • ACS8522

  • SETS Lite Synchronous Equipment Timing Source for Stratum 3/...

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Synchronous Equipment Timing Source for
Stratum 3/4E/4 and SMC Systems
ACS8522 SETS LITE
PRELIMINARY
ADVANCED COMMUNICATIONS
COMMUNICATION
Description
The ACS8522 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8522 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes, with mode selection controlled either
automatically by an internal state machine or forced by
register configuration.
The ACS8522 accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522
generates independent SEC and BITS clocks, an 8 kHz
Frame Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock, both with programmable pulse
width and polarity.
The ACS8522 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
The ACS8522 supports IEEE
scan.
1149.1
[5]
JTAG boundary
Features
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications
Meets Telcordia 1244-CORE
[19]
Stratum 3 and
GR-253
[17]
, and ITU-T G.813
[11]
Options
螜
and
螜螜
specifications
Accepts four individual input reference clocks, all with
robust input clock source quality monitoring
Simultaneously generates four output clocks, plus two
Sync pulse outputs
Absolute Holdover accuracy better than 3 x 10
-10
(manual), 7.5 x 10
-14
(instantaneous); Holdover
stability defined by choice of external XO
Programmable wander and jitter tracking/attenuation
0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface
Output phase adjustment in 6 ps steps up to
鹵 200 ns
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation. 5 V tolerant
The user can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Block Diagram
Figure 1
Block Diagram of the ACS8522 SETS LITE
T4 DPLL/Freq. Synthesis
T4 DPLL
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Selector
Input
Port
Monitors
and
Selection
Control
Optional
Divider, 1/n
n = 1 to 2
14
PFD
Digital
Loop
Filter
DTO
T4 Output
APLL
Frequency
Dividers
Output
Ports
O1
to
O4
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
T0 DPLL/Freq. Synthesis
4 x SEC
T0 DPLL
Selector
Optional
Divider, 1/n
n = 1 to 2
14
Digital
Loop
Filter
T0 Output
APLL
Frequency
Dividers
DTO
T0 Feedback
APLL
FrSync
&
MFrSync
8 kHz
(FrSync)
2 kHz
(MFrSync)
PFD
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
Serial
Port
OCXO or
TCXO
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
F8522P_001BLOCKDIA_04
Revision 1.01/December 2002 漏 Semtech Corp.
Page 1
www.semtech.com

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