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ACS8515REV2.1LC/P Datasheet

  • ACS8515REV2.1LC/P

  • Line Card Protection Switch for SONET or SDH Network Element...

  • 670.26KB

  • 50頁

  • ETC

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ADVANCED COMMUNICATIONS
Description
The ACS8515 is a highly integrated, single-chip
solution for 聭hit-less聮 protection switching of SEC
clocks from Master and Slave SETS clockcards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the in-
puts and will implement automatic system pro-
tection switching against master clock failure.
A further input is provided for an optional standby
SEC clock. The ACS8515 is fully compliant with
the required specifications and standards.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card clock, e.g.
8 kHz distributed on the back plane and
19.44 MHz generated on the line cards.
An SPI
(1)
compatible serial port is incorporated,
providing access to the configuration and status
registers for device setup.
The ACS8515 can utilise either a low cost XO
oscillator module, or a TCXO with full tempera-
ture calibration - as required by the application.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
Block Diagram
Figure 1. Simple Block Diagram
3 x S EC Input
Mas ter/Slave
+ Standby:
N x 8kHz
1.544/2.048MHz
6.48M Hz
19.44MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
MFrSync
Line Card Protection Switch
for SONET or SDH Network Elements
FINAL
Features
聲Suitable for Stratum 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
聲Meets AT&T, ITU-T, ETSI and Telcordia
specifications
聲Three SEC input clocks, from 2 kHz to
155.52 MHz
聲Generates two SEC output clocks, up to
311.04 MHz
聲Frequency translation of SEC input clock to a
different local line card clock
聲Robust input clock source frequency and
activity monitoring on all inputs
聲Supports Free-run, Locked and Holdover
modes of operation
聲Automatic 聭hit-less聮 source switchover on loss
of input
聲External force fast switch between SEC inputs
聲Phase build out for output clock phase
continuity during input switchover
聲SPI
(1)
compatible serial microprocessor interface
聲Programmable wander and jitter tracking
attenuation 0.1 Hz to 20 Hz
聲Single +3.3 V operation. +5 V I/O compatible
聲Operating temperature (ambient) -40擄C to
+85擄C
聲Available in 64 pin LQFP package
(1) SPI is a trademark of Motorola Corporation
ACS8515 Rev2.1 LC/P
3xSEC
Input
Ports
MFrSync
APLL
DPLL
Frequency Synthes is
2xSEC
Output
Ports
FrSync
MFrSync
Monitors
Frequency
Dividers
2 x S EC Output
including:
1.544/2.048MH z
3.088/4.096MH z
6.176/8.192MH z
12.352/16.384MH z
19.44MH z
38.88MH z
155.52MH z
311.04MH z
2kHz MF rSync
8kHz FrSync
Chip C lock
Generator
Priority
T able
Register
Set
SPI Compatible Serial
Microprocessor Port
TCXO or XO
Revision 1.05/December 2002
茫Semtech
Corp.
www.semtech.com

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