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ACS8510 Datasheet

  • ACS8510

  • Synchronous Equipment Timing Source for SONET or SDH Network...

  • 743.66KB

  • 69頁(yè)

  • SEMTECH   SEMTECH

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ADVANCED COMMUNCIATIONS
Description
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
Features
聲Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
聲Meets AT&T, ITU-T, ETSI and Telcordia specifi-
cations
聲Accepts 14 individual input reference clocks
聲Generates 11 output clocks
聲Supports Free-Run, Locked and Holdover
modes of operation
聲Robust input clock source quality monitoring on
all inputs
聲Automatic 聯(lián)hit-less聰 source switchover on loss
of input
聲Phase build-out for output clock phase conti-
nuity during input switchover and mode transi-
tions
聲Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EEPROM
聲Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
聲Support for Master/Slave device configuration
alignment and hot/standby redundancy
聲IEEE 1149.1 JTAG Boundary Scan
聲Single 3.3 v operation. 5 v I/O compatible
聲Operating temperature (ambient) -40擄C to
+85擄C
聲Available in 100 pin LQFP package
ACS8510 SETS
Block Diagram
14 Inp ut
Reference
Source
includin g:
AM I 64/8 kHz
2 kHz
8 kHz
N x 8 kHz
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
Input
Ports
T
OUT4
selector
Div ider
PFD
Dig ital
Loop
Filter
Output
Ports
DTO
2xT
OUT4
6xT
IN1
4xT
IN2
4xT
IN3
T
OUT0
selector
MFrSync
Monitors
DPLL/F req. Synthesis
7xT
OUT0
PFD
Div ider
Dig ital
Loop
Filter
DTO
APLL
Frequency
Dividers
DPLL/Freq. S ynthesis
T CK
TDI
TMS
T RST
TDO
MFrSync
FrSync
11 Outp ut Ports
includin g:
1.544/2.048 M Hz
3.088/4.096 M Hz
6.176/8.182 M Hz
12.352/16.384 M Hz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
AM I 64/8 kHz
2 kHz MFrSy nc
8 kHz FrSy nc
IEEE
1149.1
JTAG
Chip C lock
Generator
Priority
Table
Register
Set
Micropro cessor
Port
TCXO (*OCXO)
CLK
Revision 2.07/Jan 2001
茫2001
Semtech Corp
www.semtech.com

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