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ACS8510REV2.1 Datasheet

  • ACS8510REV2.1

  • Telecomm/Datacomm

  • 856.77KB

  • 76頁

  • ETC

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ADVANCED COMMUNICATIONS
Description
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
Block Diagram
Figure 1. Simple Block Diagram
Inp ut
Ports
2 x A MI
10 x TTL
2 x PECL/LV DS
Programmable;
64/8kHz
2kHz
4kHz
N x 8kHz
1.544/2.048MHz
6.48MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
Features
聲Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
聲Meets AT&T, ITU-T, ETSI and Telcordia
specifications
聲Accepts 14 individual input reference clocks
聲Generates 11 output clocks
聲Supports Free-Run, Locked and Holdover
modes of operation
聲Robust input clock source quality monitoring on
all inputs
聲Automatic 聭hit-less聮 source switchover on loss
of input
聲Phase build out for output clock phase
continuity during input switchover and mode
transitions
聲Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EPROM
聲Programmable wander and jitter tracking
attenuation 0.1 Hz to 20 Hz
聲Support for Master/Slave device configuration
alignment and hot/standby redundancy
聲IEEE 1149.1 JTAG Boundary Scan
聲Single +3.3 V operation, +5 V I/O compatible
聲Operating temperature (ambient) -40擄C to
+85擄C
聲Available in 100 pin LQFP package
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
ACS8510 Rev2.1 SETS
T
OUT4
selector
Div ider
PFD
Dig ital
Loop
Filter
Outp ut
Ports
DTO
DPLL/Freq. Synthesis
14xSEC
Monitors
9xS EC
T
OUT0
se lec tor
MFrSync
PFD
Div ider
Dig ital
Loop
Filter
DTO
A PLL
Frequency
Dividers
DPLL/F req. Synthesis
Chip C lock
Generator
Register
Set
M icropro cessor
Port
FrSync
MFrSync
1 x A MI
6 x TTL
2 x PECL/LV DS
Programmable:
64/8kHz
1.544/2.048MHz
3.088/4.096MHz
6.176/8.182MHz
12.352/16.384MHz
6.48MHz
19.44MHz
25.92MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
311.04MHz
2kHz MFrSync
8kHz FrSync
TCK
TDI
TMS
TRS T
TDO
IEEE
1149.1
JTAG
Priority
Table
TCXO (*OCXO)
Revision 1.04/September 2002
茫Semtech
Corp.
www.semtech.com

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