ACS573MS
January 1996
Radiation Hardened Octal
Three-State Transparent Latch
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Features
鈥?Devices QML Quali鏗乪d in Accordance with MIL-PRF-38535
鈥?Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96724 and Intersil鈥檚 QM Plan
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
鈥?SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
鈥?Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
鈥?Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current
鈮?/div>
1碌A(chǔ) at VOL, VOH
鈥?Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
GND 10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
Description
OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
The Intersil ACS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (LE) is High. When the latch goes low
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the state of
output enable.
The ACS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suf鏗亁) or a
D0
D1
D2
D3
D4
D5
D6
D7
GND
Ordering Information
PART NUMBER
5962F9672401VRC
5962F9672401VXC
ACS573D/Sample
ACS573K/Sample
ACS573HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
1
518893
File Number
4093
INTERSIL
1
2
3
4
