ACS373MS
April 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
Features
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose 300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
鈥?SEU LET Threshold >80 MEV-cm
2
/mg
鈥?Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range: -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current
鈮?碌A
at VOL, VOH
GND 10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Description
The Intersil ACS373MS is a radiation hardened octal transparent
latch with three-state outputs. The outputs are transparent to the
inputs when the latch enable (LE) is high. When the LE goes low,
the data is latched. When the Output Enable (OE) is high, the
outputs are in the high impedance state. The latch operation is
independent of the state of the output enable.
The ACS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Ordering Information
PART NUMBER
ACS373DMSR
ACS373KMSR
ACS373D/Sample
ACS373K/Sample
ACS373HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55 C to +125 C
+25
o
C
+25
o
C
+25
o
C
o
o
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Truth Table
OE
L
L
L
L
H
NOTE:
L = Low Voltage Level
H = High Voltage Level
LE
H
H
L
L
X
D
H
L
I
h
X
X = Don鈥檛 Care
Z = High Impedance State
Q
H
L
L
H
Z
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
D
COMMON
CONTROLS
LE
(11)
OE
(1)
LATCH
OE
D
Q
LE
Q
(2, 5, 6, 9, 12,
15, 16, 19)
I = Low voltage level one set-up time prior to the high to low latch enable transition
h = High voltage level one set-up time prior to the high to low latch enable transition
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
1
518799
File Number
3999
INTERSIL
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3
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