ACS125MS
January 1996
Radiation Hardened
Quad Buffer, Three-State
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 VCC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
Features
鈥?Devices QML Quali鏗乪d in Accordance with MIL-PRF-38535
鈥?Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96705 and Intersil鈥檚 QM Plan
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
鈥?SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100
鈥?Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
MEV-cm
2
/mg
RAD (Si)/s, 20ns Pulse
鈥?Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current
鈮?/div>
1碌A(chǔ) at VOL, VOH
鈥?Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
OE1
A1
Y1
OE2
A2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
OE4
A4
Y4
OE3
A3
Y3
Description
The Intersil ACS125MS is a Radiation Hardened Quad Buffer with
Three-State outputs. Each output has it鈥檚 own enable input, which when
鈥淗IGH鈥?puts the output in a high impedance state.
The ACS125MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS125MS is supplied in a 14 lead Ceramic Flatpack (K suf鏗亁) or a
Ceramic Dual-In-Line Package (D suf鏗亁).
Ordering Information
PART NUMBER
5962F9670501VCC
5962F9670501VXC
ACS125D/Sample
ACS125K/Sample
ACS125HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
File Number
1
518817
3565.1
1
2
3
4
