ACS00MS
April 1995
Radiation Hardened
Quad 2-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
Features
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose 300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
鈥?SEU LET Threshold >80 MEV-cm
2
/mg
鈥?Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range: -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current
鈮?碌A
at VOL, VOH
14 LEAD CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
Description
The Intersil ACS00MS is a Radiation Hardened quad 2-Input
NAND gate. A high logic level on both inputs forces the output
to a logic low state.
The ACS00MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radi-
ation hardened, high-speed, CMOS/SOS Logic Family.
Ordering Information
PART NUMBER
ACS00DMSR
ACS00KMSR
ACS00D/Sample
ACS00K/Sample
ACS00HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
Truth Table
INPUTS
An
L
L
H
H
Bn
L
H
L
H
OUTPUT
Yn
H
H
H
L
Functional Diagram
An
Yn
Bn
NOTE: L = Logic Level Low, H = Logic Level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
1
518813
3563.1
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