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ACEX1K Datasheet

  • ACEX1K

  • Programmable Logic Device Family

  • 86頁

  • ALTERA   ALTERA

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ACEX 1K
廬
Programmable Logic Device Family
Data Sheet
June 2001, ver. 3.1
Features...
s
s
s
s
Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
鈥?/div>
Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
鈥?/div>
Dual-port capability with up to 16-bit width per embedded array
block (EAB)
鈥?/div>
Logic array for general logic functions
High density
鈥?/div>
10,000 to 100,000 typical gates (see
Table 1)
鈥?/div>
Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
鈥?/div>
Cost-optimized process
鈥?/div>
Low cost solution for high-performance communications
applications
System-level features
鈥?/div>
MultiVolt
TM
I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
鈥?/div>
Low power consumption
鈥?/div>
Bidirectional I/O performance (setup time [t
SU
] and clock-to-
output delay [t
CO
]) up to 250 MHz
鈥?/div>
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG)
PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 MHz or 66 MHz
Table 1. ACEX
TM
1K Device Features
Feature
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
EP1K10
10,000
56,000
576
3
12,288
136
EP1K30
30,000
119,000
1,728
6
24,576
171
EP1K50
50,000
199,000
2,880
10
40,960
249
EP1K100
100,000
257,000
4,992
12
49,152
333
Altera Corporation
A-DS-ACEX-3.1
1

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  • 英文版
    Programmable Logic Device Family
    ETC
  • 英文版
    Programmable Logic Device Family
    ETC [ETC]
  • 英文版
    Programmable Logic Device Family
    ALTERA
  • 英文版
    Programmable Logic Device Family
    ALTERA [Al...
  • 英文版
    Programmable Logic Device Family
    ALTERA
  • 英文版
    Altera Corporation [Programmable Logic Family]
    ALTERA

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