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Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD 17
Typical V
OLP
(Output Ground Bounce)
<1 V at V
CC
= 5 V, T
A
= 25擄C
High-Impedance State During Power Up
and Power Down
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (鈥?2-mA I
OH
, 64-mA I
OL
)
SN54ABT16825 . . . WD PACKAGE
SN74ABT16825 . . . DL PACKAGE
(TOP VIEW)
description
The 鈥橝BT16825 devices are 18-bit buffers and line
drivers designed specifically to improve both the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices can be
used as two 9-bit buffers or one 18-bit buffer. They
provide true data.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that, if either output-enable
(OE1 or OE2) input is high, all nine affected
outputs are in the high-impedance state.
When V
CC
is between 0 and 2.1 V, the device is
power down. However, to ensure the
high-impedance state above 2.1 V, OE should be
tied to V
CC
through a pullup resistor; the minimum
value of the resistor is determined by the
current-sinking capability of the driver.
ORDERING INFORMATION
TA
鈥?0擄C to 85擄C
40擄C
鈥?5擄C to 125擄C
PACKAGE鈥?/div>
SSOP 鈥?DL
CFP鈥揥D
Tube
Tape and reel
Tube
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
GND
GND
2Y1
2Y2
GND
2Y3
2Y4
2Y5
V
CC
2Y6
2Y7
GND
2Y8
2Y9
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OE2
ORDERABLE
PART NUMBER
SN74ABT16825DL
SN74ABT16825DLR
SNJ54ABT16825WD
TOP-SIDE
MARKING
ABT16825
SNJ54ABT16825WD
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
2000, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
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