A28F200BX-T B
2-MBIT (128K x 16 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
Automotive
Y
x8 x16 Input Output Architecture
A28F200BX-T A28F200BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Optimized High Density Blocked
Architecture
One 16 KB Protected Boot Block
Two 8 KB Parameter Blocks
One 96 KB Main Block
One 128 KB Main Block
Top or Bottom Boot Locations
Extended Cycling Capability
1 000 Block Erase Cycles
Automated Word Byte Write and
Block Erase
Command User Interface
Status Register
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical I
CC
Active Current in
Static Operation
Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y
Very High-Performance Read
90 ns Maximum Access Time
45 ns Maximum Output Enable Time
Low Power Consumption
25 mA Typical Active Read Current
Deep Power-Down Reset Input
Acts as Reset for Boot Operations
Automotive Temperature Operation
b
40 C to
a
125 C
Write Protection for Boot Block
Industry Standard Surface Mount
Packaging
JEDEC ROM Compatible
44-Lead PSOP
12V Word Byte Write and Block Erase
V
PP
e
12V
g
5% Standard
ETOX
TM
III Flash Technology
5V Read
Independent Software Vendor Support
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
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Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel鈥檚 Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290500-003