廬
MULTI-DDC112 DUT BOARD FOR THE
DDC112 EVALUATION FIXTURE
By Jim Todsen and Dave Milligan
The DDC112 is capable of being daisy-chained for use in
systems with a large number of channels. To help in evalu-
ating the DDC112 in such a configuration, this Application
Bulletin describes a new DUT board designed for use with
the standard evaluation fixture DEM-DDC112U-C. This
new DUT board contains 8 DDC112s, daisy-chained to-
gether creating a 16-channel DUT board. It connects to the
PC Interface Board the same as the original single DDC112
DUT board, included with the evaluation fixture. The stan-
dard software that ships with the evaluation board can then
be used to collect data from all 8 DDC112s by a simple
modification to the setup configuration.
This Application Bulletin concentrates on the design of the
8-DDC112 DUT board. The following discussions provide
guidelines for designing a multi-DDC112 system. The basic
operation of the evaluation fixture is covered in detail in its
own data sheet (LI-500) and in Application Bulletin, AB-
125 鈥淐ustomizing the DDC112鈥檚 Evaluation Fixture.鈥?/div>
SCHEMATIC
Figure 1 shows the schematic diagram of the 8-DDC112
DUT board. It is a straightforward extension of the single-
DDC112 DUT board. The same V
REF
and digital buffering
circuits are used. The daisy chain is built by connecting one
DDC112鈥檚 DOUT pin to the next DDC112鈥檚 DIN pin. Pull-
up resistors to V
DD
should be used on DOUT. Bypass
capacitors are used at every IC to help insure clean supplies
and V
REF
. As with the original DUT board, there are socket
pins for resistors to be placed in series with the DDC112鈥檚
inputs. Voltage sources can then be connected to these
resistors using P2 and P4 to effectively generate input
current signals. When using the series resistors, make sure to
keep the resistor values high (typically 10M鈩?or greater)
and to also use high quality resistors such as Caddocks鈥?/div>
MK632 family. Standard metal-film, especially carbon re-
sistors, can introduce noise and non-linearities.
PCB LAYOUT
Table I summarizes the six layers used in the PCB. The
artwork for each of the layers is shown at a 1-to-1 scale in
Figures 2 through 7. The shields, layers 2 and 4, are identical
and therefore, are only shown once (see Figure 4). All of the
components are located on the top side.
LAYER
Silk Screen
1
2
3
4
5
6
FIGURE
2
3
4
5
4
6
7
PURPOSE
Ground Plane
Shield
Input Traces
Shield
Analog and Digital Power, V
REF
Digital Traces
Table I. PCB Layer Map.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user鈥檚 own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
漏
1999 Burr-Brown Corporation
AB-143
Printed in U.S.A. February, 1999
1
2
3
4
5
6
7
8
9
10
