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廬

The DDC112鈥檚 Test Mode

By Jim Todsen

This application bulletin covers the DDC112鈥檚 test mode. It

elaborates on the explanation given in the data sheet and is

written with the purpose of helping you use the test mode to

its fullest capability. It does assume a basic understanding of

the DDC112鈥檚 operation. For a good introduction to the

DDC112, see the DDC112鈥檚 data sheet.

The organization of this application bulletin is as follows:

First, an overview presents the basic operation of the test

mode. Next are explanations of single packet and multiple

packet test signals. Noise and linearity performance of the

test mode are then covered followed by some special consid-

erations for using the test mode. Finally, a program for

investigating test mode performance is discussed with the

listing for the program given afterwards.

the DDC112鈥檚 inputs to ground during test mode to prevent

any current from the sensor building a charge on the DDC鈥檚

inputs.

C

TEST

can be dumped once or multiple times onto the

integrator during an integration period. The next two sec-

tions explain the timing necessary to control the number of

dumps. Note that the magnitude of the test signal is not a

direct function of the integration time T

INT

, but rather the

number of charge packet dumps. If the number of charge

packets dumped remains constant, changing T

INT

will not

affect the test mode data.

C

INT

OVERVIEW

During normal operation, a sensor connected to each DDC112

input supplies signal current which is measured by DDC112

and converted to a 20-bit digital word. To help with debug

during system development and to provide a good system-

level diagnostic check, the DDC112 has a test mode which

is enabled by the TEST pin. While in test mode, the inputs

are disconnected and a test signal is measured instead.

Figure 1 shows a simplified block diagram of the front end

of the DDC112 including test mode circuitry.

You enter test mode by holding TEST HIGH while CONV

toggles. Likewise, you exit test mode by holding TEST

LOW while CONV toggles. The integration timing control

for test mode is identical to that of normal operation: CONV

still sets the side (A or B) and length of integration. As in

normal operation, there is a continuous and non-continuous

mode in test mode determined by the length of T

INT

(see

Application Bulletin AB-131 for more information on the

continuous and non-continuous modes).

C

TEST

in Figure 1 supplies the test signal to the front-end

integrators. Switches S

A

and S

B

, which in normal operation

steer the sensor鈥檚 current to the A or B integrator, are opened

and S

AT

, S

BT

and S

VT

are used instead (these switches are

only used in test mode). C

TEST

, previously charged to V

REF

by S

VT

, is dumped to the appropriate side by either S

AT

or

S

BT

depending on CONV. After the dumped charge from

C

TEST

is integrated by C

INT

, S

AT

(or S

BT

) opens and C

TEST

recharges to V

REF

via S

VT

. C

TEST

is now ready for another

charge dump. When the integration period is over, the ADC

measures the signal integrated onto C

INT

(the total test signal

dumped by C

TEST

) just as in normal operation. S

GND

shorts

S

A

S

AT

1A

S

VT

IN1

S

GND

C

TEST

V

REF

S

B

S

BT

1B

C

INT

To

ADC

C

INT

2A

S

A

S

AT

S

VT

IN2

S

GND

C

TEST

V

REF

S

B

S

BT

2B

C

INT

FIGURE 1. Simplified Block Diagram of the DDC112鈥檚

Front End.

漏

1998 Burr-Brown Corporation

AB-135

1

Printed in U.S.A. July, 1998

next

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