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CUSTOMIZING THE DDC112 EVALUATION FIXTURE
By Jim Todsen
This application note supplements the DDC112 Evaluation
Fixture data sheet (DEM-DDC112U). It provides additional
information on the operation of the PC Interface Board
(PCIB). It is intended to provide the user with information
needed to write custom software for a PC to control the
PCIB over the parallel port. This bulletin discusses the
details of the PCIB and assumes a familiarity with the basic
operation of the Evaluation Fixture. For general instructions
on how to use the DDC112 Evaluation Fixture, please refer
to the data sheet.
The heart of the DDC112 Evaluation Fixture is the PCIB. It
provides full control of DDC112, supplying the SCLK,
CONV, DCLK, etc., to the DUT board. Up to 32,768 data
points from the DDC112 can be collected in the PCIB鈥檚
RAM. During readback, the software directs the PCIB to
transfer the data from the RAM to the PC via the parallel port.
Two Xilinx Field Programmable Arrays provide the neces-
sary logic for the PCIB. Registers on these arrays determine
various settings, such as gain and integration time. Control
and readback of the DDC112 is accomplished by program-
ming these registers though the PC鈥檚 parallel port. Table I
gives the addresses and a description of each of the registers.
Figure 1 shows the PCIB RAM鈥檚 memory map. The PCIB鈥檚
schematic is shown in Figure 2. The schematics for the two
Xilinx arrays are shown in Figures 3 through 9. The logic
described in these schematics is stored in ROMs U5 and U6
on the PCIB, which automatically configure arrays U1 and
U2 on power-up. Finally, source code for an example
program is given in Listing 1.
LOCATING THE PC鈥橲 PARALLEL PORT鈥橲 ADDRESS
The PCIB communicates with the PC via the PC鈥檚 parallel
port. The address for the parallel port is found by reading the
PC鈥檚 BIOS memory. LPT1, parallel port 1鈥檚 address, is
located at hexadecimal address $40, $08 (segment, offset).
LPT2, parallel port 2鈥檚 address, is located at hexadecimal
address $40, $0A.
REGISTERS
There are 12 registers in the Xilinx arrays that are used to
configure the Evaluation Fixture. The clock speeds, integra-
tion time, gain settings, etc., of the DDC112 are controlled
through these registers. Table I lists the address and gives a
short description for each of these registers.
Before the Evaluation Fixture can be used, the registers must
be initialized as they power-up with all bits LOW. For
proper initialization, power must be applied to the DUT
漏
board before loading the registers. This insures correct align-
ment of the side A/B bit on the PCIB. This bit is used by the
software to determine the side (A or B) for each 20-bit data
from the DDC112.
An 8-bit bus is used to write data to the registers. This bus is
used for both the address and the data. The 8th bit determines
whether the bus has an address or data, and the lower 7 bits
represent either an address or data value. When LOW, the 8th
bit signals that the bus contains an address and conversely, if
HIGH, the bus contains data to be written into the addressed
register. A strobe bit latches either the address or the data on
the bus. Lines 2 through 9 of the parallel port corresponds to
U0 - U7 in Figure 2, the 8-bit bus. Line 1 of the parallel port
corresponds to STO in Figure 2, the strobe bit.
To write to a register, first send the register address on U0 - U6
with bit U7 LOW. Toggle the strobe bit, STO, from HIGH to
LOW and back to HIGH. The STO bit should be normally
held HIGH. The register address has now been selected. Send
the data to be written to the register on U0 - U6 with bit U7
HIGH and again toggle STO as before. Data will be written to
the last register addressed. It is recommended that you always
send the register address before sending the register data. This
insures you are writing to the correct register.
The valid register addresses are xxx0000 to xxx1011 (0 to
11). The lower 4 bits of the address space map to the
registers. The upper 3 bits are used in the readback process
described below. It is suggested that when writing to a
register, the upper 3 bits be set to 鈥?11鈥?
DATA COLLECTION AND READBACK FROM THE PCIB
Once the PCIB is initialized by loading the registers, it is
always in one of two modes: data collection or data readback.
Register Ctrl 1, bit 5 (鈥淲/RB鈥?in the schematics) controls
the mode: 鈥?鈥?for data collection, 鈥?鈥?for readback.
Collection
In the data collection mode, the PCIB stores data from the
DDC112 in the PCIB鈥檚 32K x 24bit RAM. Twenty of the
bits are used to store the actual DDC112 data, bit 22 stores
the side A/B bit. The other three bits are unused. Upon
sensing a negative transition in DVALID from the DDC112,
the PCIB forces DXMIT LOW after a delay set by registers,
RDLY. Two groups of twenty DCLKs per DDC112 are used
to shift the DDC112鈥檚 Channel 1 and 2 data into a shift
register. Afterwards, the data is stored in the RAM using an
8-bit bus. The RAM memory pointer is automatically
incremented after all 24 bits are stored in the RAM. All the
AB-125
Printed in U.S.A. January, 1998
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1998 Burr-Brown Corporation
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