廬
INTERFACING THE ADS7822 TO THE SYNCHRONOUS
SERIAL PORT OF THE 80x51 MICROCONTROLLER
By Gebhard Haug and Bonnie C. Baker
Analog-to-digital converters can be controlled by a normal
I/O port or with the synchronous serial port of the 80x51
microcontrollers. The synchronous serial port is more effi-
cient, however, there are some pitfalls to be aware of when
configuring the 8-pin A/D converters (ADS1286, ADS7816,
ADS7817 and ADS7822) from Burr-Brown. This applica-
tion bulletin describes how to get around these pitfalls and
get the best performance out of this combination.
The ADS1286, ADS7816, ADS7817, and ADS7822 are all
12-bit converters that are available in a variety of 8-pin
packages. These devices are classical successive approxi-
SYMBOL
t
SMPL
t
CONV
t
CYC
t
CSD
t
SUCS
t
hDO
t
dDO
DESCRIPTION
Analog Input Sample Time
Conversion Time
Throughput Rate
CS Falling to DCLOCK LOW
CS Falling to DCLOCK Rising
DCLOCK Falling to Current D
OUT
not Valid
DCLOCK Falling to Next D
OUT
Valid
mation register (SAR) A/D converters. Their architecture is
based on capacitive redistribution, which inherently in-
cludes a sample/hold function. All four of these converters
have three digital communication lines in their interface.
These communication lines are CS/SHDN, D
OUT
and
DCLOCK. The CS/SHDN pin provides a chip select func-
tion when LOW. When this pin is pulled HIGH, the A/D
converter goes into its shutdown mode. The basic timing
diagram for these A/D converters is shown in Figure 1. The
timing specifications for the individual A/D converters are
called out in Table 1.
ADS7816
1.5 (min)
2.0 (max)
12
200 (max)
0 (max)
30 (min)
15 (min)
150 (max)
ADS7817
1.5 (min)
2.0 (max)
12
200 (max)
0 (max)
30 (min)
15 (min)
150 (max)
ADS7822
1.5 (min)
2.0 (max)
12
75 (max)
0 (max)
30 (min)
15 (min)
200 (max)
UNITS
Clk Cycles
Clk Cycles
kHz
ns
ns
ns
ns
ADS1286
1.5 (typ)
12
20 (max)
0 (max)
30 (min)
15 (min)
150 (max)
TABLE I. Timing Specifications for the ADS1286, ADS7816, ADS7817, and ADS7822.
t
CYC
CS/SHDN
t
SUCS
DCLOCK
t
CSD
D
OUT
HI-Z
NULL
BIT
NULL
BIT
POWER
DOWN
HI-Z
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(1)
B11 B10
B9
B8
t
SMPL
(MSB)
t
CONV
t
DATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
t
CYC
CS/SHDN
t
SUCS
DCLOCK
t
CSD
D
OUT
HI-Z
NULL
BIT
HI-Z
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
(2)
POWER DOWN
t
SMPL
B11 B10 B9
(MSB)
t
CONV
t
DATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
t
DATA
: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. Timing Diagram for the ADS1286, ADS7816, ADS7817, and ADS7822.
漏
1997 Burr-Brown Corporation
AB-122
1
Printed in U.S.A. September, 1997
1
2
3
4
5
6
7
