廬
APPLICATION BULLETIN
INTERFACING THE ADS1210 WITH AN
8xC51 MICROCONTROLLER
By Miaochen Wu
Mailing Address: PO Box 11400, Tucson, AZ 85734 鈥?Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 鈥?Tel: (520
Telex: 066-6491 鈥?FAX (520) 889-1510 鈥?Product Info: (800) 548-6132 鈥?Internet: www.burr-brown.com/ 鈥?FAXLine: (800
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The ADS1210 is a 24-bit delta-sigma analog-to-digital con-
verter. This application bulletin provides examples of how
to interface the ADS1210 with an Intel 8xC51
microcontroller. The converter can be operated with the
serial data clock SCLK, generated by itself or provided
externally, such as by an 8xC51. The ADS1210 supports SPI
(Serial Peripheral Interface) interfacing and SSI (Synchro-
nized Serial Interface) interfacing. This bulletin focuses on
interfacing the ADS1210 to an 8xC51, which provides the
synchronous SCLK signal. The schematic and 8xC51 as-
sembly code are provided for both of the interface protocols.
DATA STRUCTURE
The ADS1210 has five internal registers; the 24-bit Data
Output Register (DOR), 8-bit Instruction Register (INSR),
32-bit Command Register (CMR), 24-bit Offset Calibration
Register (OCR) and 24-bit Full-Scale Calibration Register
(FCR). In the 8xC51, memory address from 060H to 06EH
are used to duplicate these registers. This part of memory is
called the ADS memory. The data stored in the ADS
memory are from LSB (Least Significant Bit) to MSB (Most
Significant Bit) for all the registers except INSR. Table I
shows the organization of the ADS memory.
MSB
060H
B16
B8
B0
B7
B24
B16
B8
B0
B16
B8
B0
1 Byte
DOR 2
DOR 1
DOR 0
INSR
CMR 3
CMR 2
CMR 1
CMR 0
OCR 2
OCR 1
OCR 0
RESERVED
B16
B8
06EH
B0
FCR 2
FCR 1
FCR 0
B23
B15
B7
LSB
B23
B15
B7
B0
B31
B23
B15
B7
B23
B15
B7
The INSR data is the code to instruct the ADS1210 what to do
in the next operation. Typical instruction codes are the following:
INSR = C0H
Read 3 bytes of the Data Output Register of
the ADS1210
INSR = 64H
Write 4 bytes of the Command Register of
the ADS1210
INSR = E4H
Read 4 bytes of the Command Register of
the ADS1210
This data structure is implemented in the following assem-
bly code:
DATA STRUCTURE
; The ADS1210 Instruction Register code
RD_DATA
EQU
0C0H ; INSR = Read 3 Bytes Data
WR_CMR
EQU
064H
; INSR = Write 4 Bytes CMR
RD_CMR
EQU
0E4H ; INSR = Read 4 Bytes CMR
RRD_DATA
EQU
003H
; INSR = Read 3 Bytes Data Reversed
RRD_DLSB
EQU
043H
; INSR = Read 3 Bytes Data Reversed
; with LSByte first
; Definition for delays
D1210A
EQU
8
; 256 XIN clocks with XIN=10MHz
D1210B
EQU
15
; 512 XIN clocks
D1210C
EQU
30
; 1024 XIN clocks
DSYNCD
EQU
100
; _DSYNC=L for 120碌s
; Pin connections to the ADS1210
DSYNC_
BIT
P2.5
;
CS_
BIT
P2.4
;
M_SDIO
BIT
P3.0
;
M_SCLK
BIT
P3.1
;
; Definition for flags
DRDYINT
BIT
LSByte
BIT
SLEEP
BIT
; Address for variables
AOFS
DATA
ABIT
DATA
NBYTE
DATA
NADDR
DATA
003H
004H
005H
05AH
05BH
05CH
05DH
the ADS1210 _DSYNC PIN
the ADS1210 _CS PIN
SDIO by MC51
SCLK by MC51
3
4
; _DRDY interrupt flag
; LSbyte flag
; SLEEP flag
;
;
;
;
Address offset
Address bit
INSR BYTE
INSR ADDR
TABLE I. The Memory Organization Used to Map the
ADS1210 to the 8xC51.
; Address for storing the ADS1210 register data
DOR2
DATA
060H
; DATA REG BYTE2
DOR1
DATA
061H
; DATA REG BYTE1
DOR0
DATA
062H
; DATA REG BYTE0
INSR
DATA
063H
; INSTRUCTION REG
CMR3
DATA
064H
; COMMAND REG BYTE3
CMR2
DATA
065H
; COMMAND REG BYTE2
CMR1
DATA
066H
; COMMAND REG BYTE1
CMR0
DATA
067H
; COMMAND REG BYTE0
OCR2
DATA
068H
; OFFSET COEF REG BYTE2
OCR1
DATA
069H
; OFFSET COEF REG BYTE1
OCR0
DATA
06AH ; OFFSET COEF REG BYTE0
FCR2
DATA
06CH ; GAIN COEF REG BYTE2
FCR1
DATA
06DH ; GAIN COEF REG BYTE1
FCR0
DATA
06EH ; GAIN COEF REG BYTE0
TABLE II. 8xC51 Assembly Listing鈥擟onstants and
Definitions.
漏
1997 Burr-Brown Corporation
AB-112
1
Printed in U.S.A. March, 1997
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