AB-111 Datasheet

IC型號：
AB-111
PDF描述：
AB-111 - DEM-ADS1210
文件大?。?/label>
68.67KB
PDF頁數(shù)：
6頁
芯片廠家：
ETC

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廬

APPLICATION BULLETIN

Mailing Address: PO Box 11400, Tucson, AZ 85734 鈥?Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 鈥?Tel: (520) 746-1111

Telex: 066-6491 鈥?FAX (520) 889-1510 鈥?Product Info: (800) 548-6132 鈥?Internet: www.burr-brown.com/ 鈥?FAXLine: (800) 548-6133

DEM-ADS1210/11 DEMO BOARD TRICKS TO EVALUATE

THE STEP RESPONSES OF THE ADS1211

MULTIPLEXER SWITCHING

by Bonnie Baker

One of the features of the

鈭單?/div>

Analog-to-Digital converters

like the ADS1211 and ADS1213, is the four channel, mul-

tiplexed input. This feature allows for the chip user to

individually digitize up to four separate differential signals.

This advantage can be useful in process control environ-

ments as long as the user understands the issues of latency

associated with

鈭單?/div>

converters. This application note illus-

trates the topology of the

鈭單?/div>

converter, explains the phe-

nomenon of latency in

鈭單?/div>

converters and shows its affects

on the accuracy of the digital output of the converter. The

Demo Board, DEM-ADS1210/11, is configured in such a

manner to show this behavior.

The A/D,

鈭單?/div>

converter, as shown in Figure 1, has seven

basic functional blocks. The differential, analog input signal

is sampled by the programmable gain amplifier (PGA). The

PGA stage performs the three tasks in the signal condition-

ing signal path of removing common-mode signals, gaining

the signal and consequently improving the accuracy of the

digitization process, and implementing a noise filter by use

of analog integration techniques. The PGA stage then trans-

fers the signal to the core of the

鈭單?/div>

converter. In this core

(鈭單?ADC) the signal is further conditioned in its analog state

then converted to a digital string of ones and zeros. Once the

signal is digitized, mathematical algorithms are applied to

the digital string, improving the accuracy of the conversion

even further. This process of digital manipulation is better

known as digital and/or decimation filtering.

The five remaining functional block in this converter facili-

tate the digitization process described above. The Voltage

REF and Voltage Attenuator blocks provide an analog

reference point for the front end PGA stage. The clock

provides a time reference for the digitization processes of

the

鈭單?/div>

ADC block. The

碌Controller

coordinates the digital

processes such as instructions to the

鈭單?/div>

ADC conversion

block, provides storage registers for critical offset and full-

scale measurements, and interfaces with the serial I/O inter-

face, to name a few. The serial interface communicates with

the outside digital world.

The

鈭單?/div>

converter structure has been exploited in the elec-

tronics industry for its ability to inexpensively digitize an

analog signal to a high level of accuracy. The trade-off taken

to achieve this high resolution is time. The

鈭單?/div>

digitization

process has two contributors to the time delay, also known

as latency.

漏

Clock

ADS1211 or

ADS1213

Micro Controller

Instruction Register

Command Register

Data Output Register

Offset Register

Full-Scale Register

Voltage

Attenuator

PGA

鈭嗏垜

ADC

Voltage

REF

4-chan

Mux

Serial

Interface

FIGURE 1. The ADS1210, ADS1211, ADS1212 and

ADS1213 are all

鈭單?/div>

Converters. The ADS1211 and ADS1213

are muxed versions of the ADS1210 and ADS1212, inclu-

sively. The ADS1210/11 products are higher speed

鈭單?/div>

converters that achieve up to 20 bits effective resolution at

data rates of 1kHz. The ADS1212 and ADS1213 are lower

power versions of the ADS1210 and ADS1211.

As with any conversion process, the transformation from an

analog voltage to a digital word requires a set period of time.

The time period is dependent on the system clock and the

internal settings of the gain and oversampling features in the

converter. All converter topologies, such as Successive Ap-

proximation, Pipeline, or Flash (to name a few) require time

to convert. Typically this is specified as the conversion time

by the manufacturer. When the conversion time of A/D

converter is specified by the manufacturer it is easily ac-

counted for in the system application. In the case of the

鈭單?/div>

converter, the conversion time, or latency can also be called

the data rate. Unlike the other converters mentioned above,

鈭單?/div>

converters have an additional contribution to latency,

which may or may not be an issue in the application.

1997 Burr-Brown Corporation

AB-111

Printed in U.S.A. February, 1997

型號

版本

描述

廠商

下載
AB-12

英文版

Application Bulletin AB-12

FAIRCHILD

AB-12
AB-12

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Application Bulletin AB-12

FAIRCHILD ...

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AB-102
AB-103

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AB-103 - NOISE ANALYSIS FOR HIGH SPEED OP AMPS

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AB-103
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AB-104
AB-105

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AB-105 - TUNING IN AMPLIFIERS

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AB-105
AB-106

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AB-106 - PROGRAMMING TRICKS FOR HIGHER CONVERSION SPEEDS UTI...

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