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INTERLEAVING ANALOG-TO-DIGITAL CONVERTERS
by Jerry Horn, (602) 746-7413
It is tempting when pushing the limits of analog-to-digital
conversion to consider interleaving two or more converters
to increase the sample rate (Figure 1). However, such de-
signs must take into consideration several possible sources
of error.
The first consideration is the bandwidth of the converters.
For example, if the bandwidth of the converters is just over
half their sampling rate, then it would not do much good to
interleave them. Fortunately, the bandwidth of most con-
verters which currently 鈥減ush the envelope鈥?is often many
times higher than their sample rate since these converters are
often used in undersampling situations.
The next consideration is possible offset and gain errors
between the converters. Figure 2 shows two interleaved
converters digitizing a sine wave. Converter A has an offset
problem and converter B a gain problem. The digitized
codes represent not only the original sine wave but also an
error signal. In the discrete digital domain, the error signal
is seen to contain two sine frequencies鈥攁 frequency of half
the sample rate (due to the offset error) and the other with a
frequency of half the sample rate minus the frequency of the
original input signal (due to the gain error).
The last consideration covered is the difference in INL
(integral non-linearity) between the converters. INL repre-
sents the number of LSBs the output of a converter is from
the expected output for a given input voltage. For example,
if a converter would ideally put out a code of N for an input
voltage M but actually puts out a code N+2, then the INL at
that point is two.
It is not unusual for a converter to have an INL of one or two
LSBs over a good part of its input voltage range. For
interleaving converters, the output codes could differ by as
much as two times the maximum INL (say two to four
codes) for the same input voltage. This could cause errors in
the output codes which resemble the gain and offset prob-
lems discussed earlier, and may drastically reduce the num-
ber of effective bits of the digitizing system.
+15V
Offset
+15V
Gain
鈥?5V
ADC603
(10MHz)
鈥?5V
12
L
a
t
c
h
12
2-to-1
M
U
X
12
Data
(20MHz)
12
+15V
Offset
+15V
Gain
鈥?5V
Input
D
20MHz
Clock
C
Q
Q
ADC603
(10MHz)
鈥?5V
12
L
a
t
c
h
MUX
Timing
and
Control
FIGURE 1. Two Interleaved Analog-to-Digital Converters.
漏
1994 Burr-Brown Corporation
AB-069
1
Printed in U.S.A. January, 1994
1
2
