廬
SUPERPOSITION: THE HIDDEN
DAC LINEARITY ERROR
As More DACs Become Available With Resolutions of 12 Bits and Greater, Users Should Know the
Causes and Effects of Superposition Error on Relative and Absolute Accuracy and What to Do to
Minimize It.
A digital-to-analog converter (DAC) translates digital sig-
nals to analog signals. For example, a 12-bit DAC takes a
12-bit binary number, called an input code, and converts it
into one of 4,096 analog output voltages or currents. When
the contribution to the output voltage or current of each
individual bit is independent of any other, it means that the
device exhibits no superposition error or that 鈥渟uperposition
holds.鈥?For a DAC with little or no superposition error, the
linearity error for any given code will relate to the linearity
error at some different code. This allows you to determine
the worst case linearity error, and the digital code where that
error occurs, with a very simple test.
(1)
However, if the DAC under test has excessive superposition
error, this simple test will give erroneous results; therefore,
you must test all digital codes to determine the worst case
error and code. Superposition error, or bit interaction, often
is significant in converters with a resolution of 12 to 16 bits.
If the error becomes large enough, a DAC may fail to meet
a 1/2LSB linearity error or relative accuracy specification
even with each individual bit adjusted perfectly. This speci-
fication becomes important in many applications such as
automatic test equipment or precision voltage standards
where the absolute value of the output voltage must remain
within specified limits after calibration of offset and gain
errors.
For a DAC with low superposition, the following equation
determines the output voltage, if we assume that the offset
and gain errors have been removed:
錚?/div>
b
1
(
1/2
+ 蔚
1
)
+
b
2
(
1/4
+ 蔚
2
)
+...錚?/div>
V
O
=
V
FS
錚?/div>
錚?/div>
,
錚?+
b
n
(
1/2n
+ 蔚
n
)
錚?/div>
錚?/div>
錚?/div>
(1)
where
蔚喂
x
V
FS
equals the linearity error associated with the
i
th
bit and b
i
, equals the value (0 or 1) of the i
th
bit of the DAC
input code. Since the analog output error with all input code
bits off (000...000) and all input bits on (111...111) has been
adjusted to 0 the summation of all the bit errors,
ment of that code. The linearity error (sometimes called
relative accuracy, integral linearity, nonlinearity or end-
point linearity) is defined as the maximum error magnitude
that occurs.
Now consider the relationship between the individual bit
errors (蔚
i
) and the linearity error. There exists some digital
input code (b
1
, b
2
. . . b
n
) that yields the maximum linearity
error (E
MAX
) and the one鈥檚 complement of this code (b
1
,
b
2
...b
n
), that must yield an error of the same magnitude but
in the opposite direction (鈥揈
MAX
). The relative magnitude
and polarities of the errors determine which actual input
code has the most linearity error. For the error to be maxi-
mum, all of the error terms must be additive and the
following proves true:
E
MAX
+ 鈭扙
MAX
=
b
1
蔚
1
+
b
2
蔚
2
+...
+
b
n
蔚
n
+
b
1
蔚
1
+
b
2
蔚
2
+... +b
n
蔚
n
2 E
MAX
=
b
1
+
b
1
蔚
1
+
b
2
+
b
2
蔚
2
+...
+
b
n
+
b
n
蔚
n
;
(
(
)
)
(
)
(3)
but b
i
+ b
i
= 1, making the maximum linearity error:
E
MAX
=
1/2
蔚
1
+ 蔚
2
+... + 蔚
n
.
[
]
(4)
(
蔚
1
+ 蔚
2
+ 蔚
3
...
蔚
n
)
or
錚?鈭?蔚
i
錚?/div>
,
錚?/div>
錚?/div>
錚?/div>
錚?/div>
n
i
=
i
(2)
becomes zero. This means that the errors are symmetrical or,
in other words, for every possible input code there exists an
equal and opposite error associated with the one鈥檚 comple-
This result proves interesting because it relates the maxi-
mum linearity error to the individual bit errors; therefore,
you can evaluate a DAC by simply measuring the output
error associated with n digital input codes instead of all of
the 2
n
possible combinations.
(2,3)
Stated another way, the sum of the positive bit errors should
equal in magnitude the sum of the negative bit errors when
the gain and offset errors have been removed. Any differ-
ence in these magnitudes indicates the presence of a super-
position error. If this difference proves greater than approxi-
mately 1/10 of an LSB (JDEC standard for superposition
error), further testing may become necessary to determine
the accuracy of the DAC. However, a superposition error of
more than l/10LSB does not by itself imply that a DAC
cannot meet a linearity specification of, say,
鹵l/2LSB;
it
simply means that you must conduct a more elaborate test to
determine the worst case linearity error and digital input
code where that error occurs.
漏
1983 Burr-Brown Corporation
AB-065
1
Printed in U.S.A. February, 1987
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