廬
APPLICATION BULLETIN
USING THE ADS7800 12 BIT ADC
WITH UNIPOLAR INPUT SIGNALS
By R. Mark Stitt and Dave Thomas (602) 746-7445
Mailing Address: PO Box 11400 鈥?Tucson, AZ 85734 鈥?Street Address: 6730 S. Tucson Blvd. 鈥?Tucson, AZ 85706
Tel: (602) 746-1111 鈥?Twx: 910-952-111 鈥?Telex: 066-6491 鈥?FAX (602) 889-1510 鈥?Immediate Product Info: (800) 548-6132
The ADS7800 12 bit Sampling analog-to-digital-converter
is designed to operate with bipolar inputs of
鹵5V
or
鹵10V.
With the addition of an external amplifier, the ADS7800 can
be used for 10V or 20V unipolar inputs. Four unipolar input
options are shown in this Bulletin.
ADS7800 UNIPOLAR VOLTAGE INPUT RANGES
INPUT
0
0
0
0
to
to
to
to
+10V
鈥?0V
+20V
鈥?0V
SEE FIGURE
2
3
4
5
grounded. There are four unipolar input range connections
to the ADS7800 that will produce
鹵2V
V
O
when V
1
or V
2
is
connected to an appropriate offsetting voltage instead of
ground. A summary of the four cases is shown in Table I.
INPUT RANGE
鹵5V
鹵10V
0 to +10V
0 to 鈥?0V
0 to +20V
0 to 鈥?0V
V
1
0 (Ground)
INPUT
-10.000V
+10.000V
INPUT
INPUT
V
2
INPUT
0 (Ground)
INPUT
INPUT
鈥?.000V
+5.000V
V
O
鹵2V
鹵2V
鹵2V
鹵2V
鹵2V
鹵2V
TABLE I. ADS7800 Input Ranges (see Figure 1).
The +2.0V reference output from the ADS7800 can be
amplified to provide the
鹵5V
or
鹵10V
offsetting voltage
needed. The circuits in Figures 2 to 5 show how to connect
inverting or noninverting amplifiers for the various input
ranges.
Adjustment of the offsetting voltage is required because the
absolute accuracy of the 2.0V ADS7800 reference output
may vary by a few percent. Adjust the 1k鈩?pot for an
accurate offsetting voltage (e.g. V
2
= 5.000V or V
1
=
10.000V). Even though the reference output of the ADS7800
does not have absolute accuracy, the gain of the ADC is
scaled to its value. Scaling the internal reference to generate
the offsetting voltage preserves gain accuracy with tem-
perature and supply variation so long as the R
4
/R
5
resistor ratio
tracks with temperature and a low drift op amp, such as the
OPA177, is used.
If desired, the ADC zero (negative full-scale) can be adjusted
by fine trimming the offsetting voltage with the 1k鈩?pot. To
adjust the ADC zero, apply a 1/2 LSB voltage to the input
of the ADC and adjust the gain adjust pot so the LSB output,
pin 17, toggles between 1 and 0.
The 1/2 LSB zero-adjust voltage can be derived from a
resistor divider connected to a voltage source (See Applica-
tion Bulletin AB-003, 004, and 005 for
鹵10V
references).
Remember to consider the input impedance of the ADC
when using a resistor divider. In the 10V range, the input
impedance is 2.5k鈩?+ (2.5k鈩?|| 5k鈩? = 4.17k鈩? in the 20V
range the input impedance is 5k鈩?+ (2.5k鈩?|| 2.5k鈩? =
6.25k鈩? Recommended values for a zero-adjust divider are:
INPUT RANGE
(V)
0
0
0
0
to
to
to
to
+10
鈥?0
+20
鈥?0
1/2 LSB
(V)
0.012
鈥?.012
0.024
鈥?.024
V
REF
(V)
+10.00
鈥?0.00
+10.00
鈥?0.00
R
D1
(k鈩?
8.25
8.25
4.12
4.12
R
D2
(鈩?
10.0
10.0
10.0
10.0
To understand how the circuits work, consider the ADS7800
input voltage divider network shown in Figure 1. Since the
input resistor divider network drives a high impedance at
V
O
, the transfer function is:
V
O
=
R
3
(R
2
V
1
+ R
1
V
2
)
R
1
R
2
+ R
1
R
3
+ R
2
R
3
since R
2
= R
3
and R
1
= 2 R
2
,
V
O
=
V
1
+ 2 V
2
5
Where:
V
1
= voltage at pin 1 (V)
V
2
= voltage at pin 2 (V)
V
O
= voltage into ADC cell (V)
ADS7800
1
R
1
5k
鈩?/div>
R
2
2.5k
鈩?/div>
R
3
2.5k
鈩?/div>
4
鹵2V V
O
to ADC
12 Bits
Out
V
1
V
2
2V Ref
Out
2
3
FIGURE 1. ADS7800 Input-Voltage Scaling Resistor Net-
work.
The internal ADC gives a zero to full-scale digital output
with
鹵2V
at V
O
(the internal ADC node voltage shown in
Figure 1). When used in the standard bipolar voltage input
mode, with V
2
= 0 (i.e. V
2
connected to analog ground),
鹵10V
input at pin 1 of the ADS7800 produces
鹵2V
output at V
O
.
Similarly,
鹵5V
input at pin 2 produces
鹵2V
V
O
with V
1
漏
1990 Burr-Brown Corporation
AB-019A
Printed in U.S.A. February, 1991
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