Data Sheet
29319.47E
A3949
DMOS Full-Bridge Motor Driver
A3949SLB SOIC
N/C
MODE
PHASE
GND
SLEEP
ENABLE
1
2
3
4
5
6
7
8
16 N/C
15 VREG
14 VCP
13 GND
12 CP2
11
CP1
Designed for PWM (pulse width modulated) control of dc motors, the
A3949 is capable of peak output currents to 鹵2.8 A and operating volt-
ages to 36 V.
PHASE and ENABLE input terminals are provided for use in control-
ling the speed and direction of a dc motor with externally applied PWM
control signals. Internal synchronous recti鏗乧ation control circuitry is
provided to reduce power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with hysteresis,
undervoltage monitoring of V
BB
and V
CP
, and crossover current protec-
tion.
The A3949 is supplied in a choice of two power packages, a 16-pin
plastic SOIC with a copper batwing tab (part number suf鏗亁
LB),
and
a low pro鏗乴e (1.1mm) 16-pin TSSOP (suf鏗亁
LP)
with exposed power
tab. Both packages are available in a lead-free version (100% matte tin
leadframe).
Scale 1:1
OUTA
SENSE
10 OUTB
9
VBB
A3949SLP TSSOP
N/C
MODE
PHASE
GND
SLEEP
1
2
3
4
5
6
7
8
16 N/C
15 VREG
14 VCP
13 GND
12 CP2
11 CP1
10 OUTB
9 VBB
Scale 1:1
ENABLE
OUTA
SENSE
FEATURES
Single supply operation
Very small outline package
Low R
DS(ON)
outputs
Sleep function
Internal UVLO
Crossover current protection
Thermal shutdown protection
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage
V
BB
...............................................................36
V
V
BB
(Peak < 2
渭s)
........................................38
V
Output Current, I
OUT
(Repetitive)
1
....................鹵2.8
A
Sense Voltage, V
SENSE
.........................................0.5
V
Logic Input Voltage, V
IN
......................鈥?.3
V to 7 V
Package Power Dissipation, P
D
A3949SLB
2
.........................................
52潞C / W
A3949SLP
3
..........................................
34潞C / W
Operating Temperature Range
Ambient Temperature, T
A
............鈥?0擄C
to +85擄C
Junction Temperature, T
J
.................+150擄C
Max.
Storage Temperature, T
S
...........鈥?5擄C
to +150擄C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions,
DO NOT
exceed the speci鏗乪d I
OUT
or T
J
.
2
Measured on a typical two-sided PCB with 2 in.
2
copper
ground plane.
3
Measured on a JEDEC-standard "High-K" 4-layer PCB.
1
Use the following complete part numbers when ordering:
Part Number
A3949SLB-T
A3949SLBTR-T
A3949SLP-T
A3949SLPTR-T
*
Pb-free
*
Yes
Yes
Yes
Yes
Package
16-pin, SOIC
16-pin, SOIC
16-pin, TSSOP
16-pin, TSSOP
Packing
47 per tube
1000 per reel
96 per tube
4000 per reel
Pb-based variants are being phased out of the product line. The variants cited
in this footnote are in production but have been determined to be LAST TIME
BUY. This classi鏗乧ation indicates that sale of this device is currently restricted
to existing customer applications. The variants should not be purchased for
new design applications because obsolescence in the near future is probable.
Samples are no longer available. Status change: October 31, 2006. Deadline
for receipt of LAST TIME BUY orders: April 27, 2007. These variants include:
A3949SLB, A3949SLBTR, A3949SLP, and A3949SLPTR.
ALLEGRO
1
2
3
4
5
6
7
8
