A2111
Preliminary Product Brief
Skyhawk
10 Gigabit Ethernet LAN/WAN PHY
Overview
The Skyhawk is a highly integrated, ultra-low-power
frame processing solution for 10 Gigabit Ethernet (10
GbE) physical layer applications. The device provides
complete PCS-R, PCS-W, and WIS functionality and
can operate as a 10 GbE LAN or WAN PHY.
In 10 GbE WAN PHY mode, the line-side supports a
standard 16-bit, 622.08 MHz XSBI / SFI-4 interface. In
10 GbE LAN PHY mode, the line-side supports a
standard 16-bit, 644.53 MHz XSBI interface. The
system-side interface is a selectable standard HSTL
XGMII or SSTL-2 XGMII interface.
PCS layer functions include 64b/66b encoding and
decoding, X
58
scrambling and descrambing, gear box-
ing, and rate matching. Block-lock detection and
remote and local fault handling are also supported.
WIS functions include WIS framing, pointer process-
ing, and X
7
scrambling and descrambling, as well as
error rate monitoring and alarm processing per ANSI
T1-416 鈥?1999.
For device control and configuration, the Skyhawk pro-
vides a standard 32-bit processor interface, as well as a
Management Data I/O (MDIO) interface and MDIO
registers. The device conforms to the IEEE serial
LAN-PHY and WAN-PHY proposals.
A key application for the device is to facilitate
cost-effective interfacing between standard 10 Gbps
optical modules with XSBI interfaces and link layer
devices with XGMII interfaces. Other applications
include optical core routers, enterprise switches, and
Ethernet line terminating equipment.
Block Diagram
XSBI /
SFI-4
TX
Optical
I/F
WIS
Framer
TX
10 GbE
Data
Engine
TX
XGMII
I/F
XGMII (HSTL)
XGMII (SSTL-2)
Optical
Loopback
WIS
Loopback
WIS Bypass for LAN PHY
WIS Bypass for LAN PHY
PCS
Loopback
System
Loopback
XSBI /
SFI-4
RX
Optical
I/F
WIS
Framer
RX
10 GbE
Data
Engine
RX
XGMII
I/F
XGMII (HSTL)
XGMII (SSTL)
CPU I/F
MDIO
CPU
Confidential and Proprietary
Ample Communications
4034 Clipper Court 鈥?Fremont, CA 94538
Phone: 510-657-1500 鈥?Email: info@amplecomm.com
7/8/02
1
2
