Switching
Solutions
Prestera
廬
-EX116
IPv6-Enabled 48 Fast Ethernet
+ 4 Gigabit Ethernet Packet Processor
98EX116
PRODUCT OVERVIEW
The Marvell
簍
Prestera
簍
-EX family of packet processors delivers multi-layer enterprise switching with exceptional
performance and industry-leading features. The Prestera-EX116 integrates 48 Fast Ethernet (FE) ports, 4
Gigabit Ethernet (GbE) ports and a 16 Gbps uplink bus for uncompromising, non-blocking performance and
system scalability. This complete system-on-chip (SoC) devices support line rate IPv6/IPv4 Unicast & Multicast
Routing, IP-in-IP Tunneling, L2 Bridging support along with advanced L2-L4 Traffic Classification, Filtering,
and Prioritization. The 98EX116 device provides the ideal solution for rapid development of high-port density
FE chassis, stackable and standalone switching systems with Gigabit uplinks. The Prestera-EX family
provides a complete line of FE, GbE and 10 GbE switching solutions with 100% software compatibility
across the product line.
Uplink Bus
Uplink Interface
CPU
SecureControl
PCI
DDR-SDRAM
CPU Interface
Buffer DRAM Interface
Scheduling & sFlow
Egress Processing
UC/MC Routing Tables
On Chip TCAMs
ARP/MAC VLAN Tables
12 Ports GbE RGMII
IPv4/6 Routing
External SRAM Interface
Traffic Management
Policy Engine
L2 Engine
DDR-SDRAM
IPv4/IPv6
Memory
IPv6
Memory
Buffer
SDRAM
Alaska
簍
Gigabit PHY
Fig 1. Prestera Packet Processor (98EX116) Block Diagram
SPECIAL FEATURES
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IPv6
脨 Line rate IPv6 Unicast routing
脨 Line rate IPv6 Multicast routing
脨 IP-in-IP tunneling
脨 Address scope checking
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Marvell Policy Control Lists
脨 On-chip TCAM
脨 48 byte-wide match key with logical offsets
脨 Dual Policy lookup with individual actions
脨 Comprehensive list of Policy Action Entities
脨 Multiple TCAM lookup modes
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SecureControl
脨 8 priority queues for To-CPU & From-CPU packets
脨 Advanced scheduling and rate limiting of CPU-bound packets
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Distributed Switching Architecture (DSA)
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Forty-eight 10/100 Mbps Ethernet ports with SSMII interfaces
and four 10/100/1000 Mbps Ethernet ports with RGMII interfaces
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High-performance uplink bus
BENEFITS
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Future-proof networks with hardware support for IPv6
脨 Performance for enterprise & service provider deployments
脨 Purpose-built for peer-peer & multimedia applications
脨 Best-in-class support for IPv6-IPv4 co-existence and migration
脨 For Layer 3 forwarding security with line rate performance
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State-of-art security via Packet Classification and Control
脨 Provides optimized and deterministic behavior
脨 Precise user defined keys, full support for IPv6 rules
脨 Granular classification with easier rule table management
脨 For granular control over packet forwarding
脨 For efficient use of TCAM and increased number of policies
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Enables best-in-class high availability feature set
脨 Enables prioritization and control of CPU traffic
脨 Prevents Denial of Service attacks on CPU
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Permits design of value line cards and systems with Marvell
Prestera DX and Link Street
簍
SOHO devices
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For high port density, small form factor FE switching solutions
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Enables design of chassis and stackable systems by connecting
with Prestera FX family of fabric processors
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