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89PES5T5 Datasheet

  • 89PES5T5

  • 5-Lane 5-Port PCI Express Switch

  • 26頁

  • IDT

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5-Lane 5-Port PCI Express廬
Switch
廬
89PES5T5
Data Sheet
Advance Information*
Device Overview
鈼?/div>
The 89HPES5T5 is a member of IDT鈥檚 PRECISE鈩?family of PCI
Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
鈼?/div>
鈼?/div>
Features
鈼?/div>
鈼?/div>
High Performance PCI Express Switch
鈥?Five 2.5Gbps PCI Express lanes
鈥?Five switch ports
鈥?Upstream port is x1
鈥?Downstream ports are x1
鈥?Low-latency cut-through switch architecture
鈥?Support for Max Payload Sizes up to 256 bytes
鈥?One virtual channel
鈥?Eight traffic classes
鈥?PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion
鈥?Ability to load device configuration from serial EEPROM
Legacy Support
鈥?PCI compatible INTx emulation
鈥?Bus locking
鈼?/div>
鈼?/div>
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates five 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
鈥?Supports ECRC and Advanced Error Reporting
鈥?Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
鈥?Compatible with Hot-Plug I/O expanders used on PC mother-
boards
Power Management
鈥?Utilizes advanced low-power design techniques to achieve low
typical power consumption
鈥?Supports PCI Power Management Interface specification (PCI-
PM 1.2)
鈥?Unused SerDes are disabled.
鈥?Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
鈥?Built in Pseudo-Random Bit Stream (PRBS) generator
鈥?Numerous SerDes test modes
鈥?Ability to read and write any internal register via the SMBus
鈥?Ability to bypass link training and force any link into any mode
鈥?Provides statistics and performance counters
Block Diagram
5-Port Switch Core / 5 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
Mux / Demux
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
(Port 4)
(Port 5)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 26
漏
2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
September 7, 2007
Advance Information

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